MPC8280 datasheet(902/1386 Pages) FREESCALE

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Multi-Channel Controllers (MCCs)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

29-12

Freescale Semiconductor

29.3.2.1

Internal Transmitter State (TSTATE)—Transparent Mode

In transparent mode, TSTATE functions the same as in HDLC mode. For a description, refer to

Section 29.3.1.1, “Internal Transmitter State (TSTATE)—HDLC Mode.”

29.3.2.2

Interrupt Mask (INTMSK)—Transparent Mode

In transparent mode, INTMSK functions the same as in HDLC mode. For a description, refer to Section

29.3.2.2.

29.3.2.3

Channel Mode Register (CHAMR)—Transparent Mode

Figure 29-6 shows the user-initialized channel mode register, CHAMR, for transparent mode. For

channels that are used in conjunction with CES functionality, the user should refer to Section 29.3.3.2,

“Channel Mode Register (CHAMR)—AAL1 CES,” for additional information.

0x30

RBDFlags Hword RxBD flags, used by the CP (read-only for the user)

0x32

RBDCNT

Hword Rx internal byte count. Number of remaining bytes in buffer, used by the CP (read-only

for the user)

0x34

RBDPTR

Word

Rx internal data pointer. Points to current absolute data address of channel, used by the

CP (read-only for the user)

0x38

TMRBLR

Hword Transparent maximum receive buffer length. Defines the maximum number of bytes

written to a receiver buffer before moving to the next buffer for the respective channel.

This value must be 8 byte aligned.

0x3A

RCVSYNC Hword Receive synchronization pattern. Defines the synchronization pattern when

CHAMR[SYNC] is 0b1x. The two bytes are checked in reverse order (byte from address

0x3B first and byte from address 0x3A last). Non-inverted data is used for

synchronization even if the channel is programmed to invert the data. Clear RCVSYNC

when CHAMR[SYNC] = 0b0x.

0x3C

—

Word

Reserved

1 The offset is relative to dual-port RAM address 64*CH_NUM

123456789

Field MODE

POL

SYNC

—

RQN

—

Reset

—

R/W

Offset

0x1A

Figure 29-6. Channel Mode Register (CHAMR)—Transparent Mode

Table 29-6. Channel-Specific Parameters for Transparent Operation (continued)

Offset1

Name

Width

Description

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