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MPC8280 Datasheet(PDF) 900 Page - Freescale Semiconductor, Inc

Part # MPC8280
Description  PowerQUICC??II Family Reference Manual
PDF  1386 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8280 Datasheet(HTML) 900 Page - Freescale Semiconductor, Inc

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Multi-Channel Controllers (MCCs)
MPC8280 PowerQUICC II Family Reference Manual, Rev. 1
29-10
Freescale Semiconductor
29.3.1.4
Internal Receiver State (RSTATE)—HDLC Mode
Internal receiver state (RSTATE) is a 4-byte register that provides transaction parameters associated with
SDMA channel accesses (like function code registers) and starts the receiver channel.
To start the channel the user must write 0xHH800000 to RSTATE, where HH is the RSTATE high byte
(see Figure 29-5). When the channel is active the CP changes the value of the 3 LSBs, hence these 3 bytes
must be masked if the user reads back the RSTATE.
RSTATE high-byte fields are described in Table 29-5.
01234567
Field
—
GBL
BO
TC2
DTB
BDB
Reset
—
R/W
R/W
Addr
0x20
Figure 29-5. Rx Internal State (RSTATE) High Byte
Table 29-5. RSTATE High-Byte Field Descriptions
Bits
Name
Description
0–1
—
Reserved, should be cleared.
2
GBL
Global. Setting GBL activates snooping (only the 60x bus can be snooped, this parameter is ignored
for local bus transactions).
3–4
BO
Byte ordering. Set BO to select the required byte ordering for the buffer. If BO is changed on-the-fly,
it takes effect at the beginning of the next frame or at the beginning of the next BD.
00 Reserved
01 Munged little-endian.
1x Big-endian
5
TC2
Transfer code. Contains the transfer code value of TC[2], used during this SDMA channel memory
access. TC[0–1] is driven with a 0b11 to identify this SDMA channel access as a DMA-type access.
6
DTB
Data bus indicator.
The transfers to data buffers are handled by the:
0 60x bus SDMA
1 Local bus SDMA
7
BDB
BD and interrupt circular tables bus indicator.
The transfers to/from BD and interrupt circular tables are handled by the:
0 60x bus SDMA
1 Local bus SDMA
Note: The following restrictions result from the fact that there is a common bus selection bit for BDs
and interrupt circular tables:
• The RxBDs of all the channels that use a particular interrupt table must reside on the same bus
(60x or local).
• All TxBDs must reside on the same bus (60x or local).



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