MPC8280 datasheet(927/1386 Pages) FREESCALE

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Multi-Channel Controllers (MCCs)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

29-37

29.8.1.1

Interrupt Circular Table Entry

Each interrupt circular table entry, shown in Figure 29-20, contains information about channel-specific

events. The transmit circular table shows only events caused by transmission; the receive circular tables

shows only events caused by reception. The corresponding interrupt mask bits are mode-dependent; refer

to the appropriate section:

•

Section 29.3.1.2, “Interrupt Mask (INTMSK)—HDLC Mode”

•

Section 29.3.2.2, “Interrupt Mask (INTMSK)—Transparent Mode”

•

Section 29.3.3.1.1, “Interrupt Circular Table Entry and Interrupt Mask (INTMSK) —AAL1 CES”

•

Section 29.3.4.1, “Extended Channel Mode Register (ECHAMR)—SS7 Mode”

Table 29-19 describes interrupt circular table fields.

Field

OCT1

1 SS7 mode only. Otherwise, reserved.

SUERM1 FISU1

—

TXB

—

AERM1 NID

IDL

MRF RXF

BSY

RXB

—

—SLIPE2

2 Only used in conjunction with AAL1 CES.

SLIPS2

—

R/W

Field

—

Channel Number

—

R/W

Figure 29-20. Interrupt Circular Table Entry

Table 29-19. Interrupt Circular Table Entry Field Descriptions

Bits

Name

Description

Valid bit. V = 1 indicates that this entry contains valid interrupt information. Upon generating a new entry,

the CP sets V = 1. The user clears V immediately after it reads the interrupt flags of the entry (before

processing the interrupt). The V bits in the table are user-initialized. During initialization, the user must

clear those bits in all table entries.

Wrap bit. W = 1 indicates the last interrupt circular table entry. The next event’s entry is written/read (by

CP/user) from the address contained in INTBASE (see Table 29-1 on page 29-4). During initialization,

the user must clear all W bits in the table except for the last one which must be set.

—

Reserved, should be cleared. (If SS7 mode, refer to the following description.)

OCT

SS7 mode only: N octets received. If the channel is in octet counting, this bit is set when N octets have

been received.

—

Reserved, should be cleared. (If SS7 mode, refer to the following description.)

SUERM

SS7 mode only: SU error monitor threshold reached. The SU error monitor has reached the

programmed threshold T.

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