MPC8280 datasheet(926/1386 Pages) FREESCALE

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Multi-Channel Controllers (MCCs)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

29-36

Freescale Semiconductor

29.8.1

MCC Event Register (MCCE)/Mask Register (MCCM)

The MCC event register (MCCE) is used to report events and generate interrupt requests. For each of its

flags, a programmable mask/enable bit in MCCM determines whether an interrupt request is generated.

The MCC mask register (MCCM) is used to enable/disable interrupt requests. For each flag in the MCCE

there is a programmable mask/enable bit in MCCM which determines whether an interrupt request is

generated. Setting an MCCM bit enables and clearing an MCCM bit disables the corresponding interrupt.

MCCE bits are cleared by writing ones to them; writing zeros has no effect.

Figure 29-19 shows MCCE and MCCM bits.

Table 29-18 describes MCCE fields.

131415

Field QOV0 RINT0 QOV1 RINT1 QOV2 RINT2 QOV3 RINT3

—

TQOV TINT GUN GOV

Reset

0000_0000_0000_0000

R/W

Addr

0x11B30 (MCCE1), 0x11B50 (MCCE2)/0x11B34 (MCCM1), 0x11B54 (MCCM2)

Figure 29-19. MCC Event Register (MCCE)/Mask Register (MCCM)

Table 29-18. MCCE/MCCM Register Field Descriptions

Bits

Name

Description

QOV0

QOVx—Receive interrupt queue overflow. IQOV is set (and an interrupt request generated) by the CP

whenever an overflow occurs in the transmit circular interrupt table. This occurs if the CP tries to update an

interrupt entry that was not handled by the user (such an entry is identified by V = 1).

RINTx—Receive interrupt. When RINT = 1, the MCC generated at least one new entry in the receive

interrupt circular table. After clearing it, the user reads the next entry from the receive interrupt circular table

and starts processing a specific channel’s exception. The user returns from the interrupt handler when it

reaches a table entry with V = 0.

1RINT0

2QOV1

3RINT1

4QOV2

5RINT2

6QOV3

7RINT3

8–11

—

Reserved, should be cleared.

TQOV

Transmit interrupt queue overflow. TQOV is set (and interrupt request generated) by the CP whenever an

overflow occurs in the transmit circular interrupt table. This condition occurs if the CP attempts to write a

new interrupt entry into an entry that was not handled by the user. Such an entry is identified by V = 1.

TINT

Transmit interrupt. When TINT = 1, at least one new entry in the transmit interrupt circular table was

generated by MCC. After clearing it, the user reads the next entry from the transmit interrupt circular table

and starts processing a specific channel’s exception. The user returns from the interrupt handler when it

reaches a table entry with V = 0.

GUN

Global transmit underrun. This flag indicates whether an underrun occurred inside the MCC’s transmit FIFO

array (see Section 29.8.1.2, “Global Transmitter Underrun (GUN)”). The user must clear this bit.

GOV

Global receiver overrun. This flag indicates whether an overrun occurred inside the MCC’s receive FIFO

array (see Section 29.8.1.4, “Global Overrun (GOV)”). The user must clear this bit.

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