MPC8280 datasheet(925/1386 Pages) FREESCALE

925 / 1386 page

Multi-Channel Controllers (MCCs)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

29-35

Figure 29-18. Interrupt Circular Table

There is one table for transmitter interrupts and from one to four tables for receiver interrupts. Each

channel is programmed to report receiver interrupts in one of the receiver tables. This way receiver

interrupts can be sorted, for example, by priority. Each interrupt circular table must be least two entries

long.

T/RINTBASE and T/RINTPTR, which are user-initialized global MCC parameters (See Section 29.2,

“Global MCC Parameters”), point to the starting location of the table (in external memory) and the current

empty position (initialized at the top of the table) available to the CP. All the entries in the table must be

user-initialized with 0x00000000, except for the last one which must be initialized with 0x40000000 (W

= 1, thus defining the end of the table). When an MCC channel generates an interrupt request, the CP writes

a new entry to the table (with V = 1) and increments T/RINTPTR (if W = 1 for the current entry,

T/RINTPTR is loaded with T/RINTBASE).

The circular interrupt tables consist of channel-specific events, with a bit for each possible event as well

as the number of the channel reporting that event. Each channel has an INTMSK field that determines

which events on that particular channel trigger the creation of a new entry in the interrupt tables. Whenever

a new entry is added to an interrupt table, the MCC will set the appropriate TINT or RINTx bit in the

MCCE global event register, if that bit is properly enabled in MCCM global mask register. If there was no

room in the interrupt table for a new entry the corresponding queue overflow (QOVx) bit will be set in the

MCCE and the interrupt information is lost although operation will continue.

After an MCC interrupt reaches the core, the software should read the corresponding MCCE. After

clearing the appropriate event bits by writing ones to them, the software may begin processing the table(s)

that contain pending events, as indicated by the bits MCCE[RINTx] and MCCE[TINT]. When processing

the interrupt tables, the software must clear each entry’s valid bit (V) (see Section 29.8.1.1, “Interrupt

Circular Table Entry”). The user follows this procedure until it reaches an entry with V = 0. It may not be

appropriate for an application to process every new entry of all interrupt tables at once, depending on

desired interrupt handler latency or other factors. It is up to the user to determine an interrupt handling

scheme that provides desired performance and functionality.

V=0

W=0

Interrupt Flags

Channel Number

T/RINTBASE

V=0

W=0

Interrupt Flags

Channel Number

V=0

W=0

Interrupt Flags

Channel Number

V=0

W=0

Interrupt Flags

Channel Number

V=1

W=0

Interrupt Flags

Channel Number

V=1

W=0

Interrupt Flags

Channel Number

V=0

W=0

Interrupt Flags

Channel Number

V=0

W=0

Interrupt Flags

Channel Number

V=0

W=1

Interrupt Flags

Channel Number

T/RINTPTR

Software Pointer

2–17

18–25

26–31

Interrupt Circular Table Entry

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