MPC8280 datasheet(1042/1386 Pages) FREESCALE

1042 / 1386 page

ATM Controller and AAL0, AAL1, and AAL5

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

31-82

Freescale Semiconductor

Table 31-44 describes UTOPIA master mode signals.

31.12.1.1 UTOPIA Master Multiple PHY Operation

The MPC8280 supports two polling modes:

•

Direct polling uses CLAV[3–0] with PHY selection using ADD[1–0]. Up to four PHYs can be

supported.

Table 31-44. UTOPIA Master Mode Signal Descriptions

Signal

Description

TxDATA[15–0]/[7–0]

Carries transmit data from the ATM controller to a PHY device. TxDATA[15]/[7] is the msb when

using UTOPIA 16/8, TxDATA[0] is the lsb.

TxSOC

Transmit start of cell. Asserted by the ATM controller when the first byte of a cell is sent on

TxDATA lines.

TxENB

Transmit enable. Asserted by the ATM controller when valid data is placed on the TxDATA lines.

TxClav/TxCLAV[3–0]

Transmit cell available. Asserted by the PHY device to indicate that the PHY has room for a

complete cell.

TxPRTY

Transmit parity. Asserted by the ATM controller. It is an odd parity bit over the TxDATA bits.

TxCLK

Transmit clock. Provides the synchronization reference for the TxDATA, TxSOC, TxENB,

TxCLAV, TxPRTY signals. All the above signals are sampled at low-to-high transitions of

TxCLK.

TxADD[4–0]

Transmit address. Address bus from the ATM controller to the PHY device used to select the

appropriate M-PHY device. Each M-PHY device needs to maintain its address. TxADD[4] is the

msb.

RxDATA[15–0]/[7–0]

Carries receive data from the PHY to the ATM controller. RxDATA[15]/[7] is the msb when using

UTOPIA 16/8, RxDATA[0] is the lsb.

RxSOC

Receive start of cell. Asserted by the PHY device as the first byte of a cell is received on

RxDATA.

RxENB

Receive enable. An ATM controller asserts to indicate that RxDATA and RxSOC will be sampled

at the end of the next RxCLK cycle. For multiple PHYs, RxENB is used to three-state RxDATA

and RxSOC at each PHY’s output. RxDATA and RxSOC should be enabled only in cycles after

those with RxENB asserted.

RxClav/RxCLAV[3–0]

Receive cell available. Asserted by a PHY device when it has a complete cell to give the ATM

controller.

RxPRTY

Receive parity. Asserted by the PHY device. It is an odd parity bit over the RxDATA. If there is

a RxPRTY error and the receive parity check FPSMR[RxP] is cleared, the cell is discarded. See

Section 31.13.2, “FCC Protocol-Specific Mode Register (FPSMR),” and Section 31.10.7, “UNI

Statistics Table.”

RxCLK

Receiver clock. Synchronization reference for RxDATA, RxSOC, RxENB, RxCLAV, and

RxPRTY, all of which are sampled at low-to-high transitions of RxCLK.

RxADD[4–0]

Receive address. Address bus from the ATM controller to the PHY device used to select the

appropriate M-PHY device. Each M-PHY device needs to maintain its address. RxADD[4] is the

msb.

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