MPC8280 datasheet(1043/1386 Pages) FREESCALE

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ATM Controller and AAL0, AAL1, and AAL5

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

31-83

•

Single CLAV polling uses Clav and ADD[4–0]. ATM controller polls all active PHYs starting from

PHY address 0x0 to the address written in FPSMR[LAST_PHY]. Up to 31 PHY devices are

supported.

Both modes support round-robin priority or fixed priority, described in Section 31.13.2, “FCC

Protocol-Specific Mode Register (FPSMR).”

31.12.2 UTOPIA Interface Slave Mode

In UTOPIA slave mode (single or multiple PHY), cells are transferred using cell-level and octet-level

handshakes as defined by the UTOPIA level-2 standard. The FCC allows cell transfer to be halted or

paused. If the master negates TXENB, the cell that the FCC is transmitting is halted. If the master negates

RXENB, the cell that the FCC is receiving is paused. Note the following restriction on halting a cell

transfer: there cannot be a halt immediately before the transfer of the last data word. There is no restriction

on pausing a cell transfer.

UTOPIA slave signals are shown in Figure 31-58.

Figure 31-58. UTOPIA Slave Mode Signals

Table 31-45 describes UTOPIA slave mode signals.

Table 31-45. UTOPIA Slave Mode Signals

Signal

Description

TxDATA[15–0]/[7–0]

Transmit data bus. Carries transmit data from the ATM controller to the master device.

TxDATA[15]/[7] is the msb, TxDATA[0] is the lsb.

TxSOC

Transmit start of cell. Asserted by an ATM controller as the first byte of a cell is sent on the

TxDATA lines.

TxENB

Transmit enable. An input to the ATM controller. It is asserted by the UTOPIA master to signal

the slave to send data in the next TxCLK cycle.

TxCLAV

Transmit cell available. Asserted by the ATM controller to indicate it has a complete cell to

transmit.

TxPRTY

Transmit parity. Asserted by the ATM controller. It is an odd parity bit over the TxDATA.

TXDATA[15–0]/[7–0]

TXSOC

TXENB

TXPRTY

TXCLK

TXCLAV

TXADD[4–0]

MPC8280

RXDATA[15–0]/[7–0]

RXSOC

RXENB

RXPRTY

RXCLK

RXCLAV

RXADD[4–0]

MPC8280

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