MPC8280 datasheet(1040/1386 Pages) FREESCALE

1040 / 1386 page

ATM Controller and AAL0, AAL1, and AAL5

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

31-80

Freescale Semiconductor

31.11.2 Interrupt Queue Entry

Each one-word interrupt queue entry provides detailed interrupt information to the host. Figure 31-56

shows an entry.

Table 31-42 describes interrupt queue entry fields.

31.11.3 Interrupt Queue Parameter Tables

The interrupt queue parameters are held in parameter tables in the dual-port RAM; see Table 31-43.

INTT_BASE in the parameter RAM points to the base address of these tables. Each of the four interrupt

queues has its own parameter table with a starting address given by INTT_BASE+ RCT/TCT[INTQ]

× 16.

34567

Offset + 0x00

—

TBNR RXF BSY TXB RXB

Offset + 0x02

Channel Code (CC)

Figure 31-56. Interrupt Queue Entry

Table 31-42. Interrupt Queue Entry Field Description

Offset

Bits

Name

Description

0x00

Valid interrupt entry

0 This interrupt queue entry is free and can be use by the CP.

1 This interrupt queue entry is valid. The host should read this interrupt and clear this bit.

—

Reserved, should be cleared.

Wrap bit. When set, this is the last interrupt circular table entry. During initialization, the

host must clear all W bits in the table except the last one, which must be set.

3–10

—

Reserved, should be cleared.

TBNR

Tx buffer-not-ready. Set when a transmit buffer-not-ready interrupt is issued. This interrupt

is issued when the CP tries to open a TxBD that is not ready (R = 0). This interrupt is sent

only if TCT[BNM] = 1. This interrupt has an associated channel code.

Note that for AAL5, this interrupt is sent only if frame transmission is started. In this case,

an abort frame transmission is sent (last cell with length=0), the channel is taken out of the

APC, and the TCT[VCON] flag is cleared.

RXF

Rx frame. RXF is set when an Rx frame interrupt is issued. This interrupt is issued at the

end of AAL5 PDU reception. This interrupt is issued only if RCT[RXFM] = 1. This interrupt

has an associated channel code.

BSY

Busy condition. The BD table or the free buffer pool associated with this channel is busy.

Cells were discarded due to this condition. This interrupt has an associated channel code.

TXB

Tx buffer. TXB is set when a transmit buffer interrupt is issued. This interrupt is enabled

when both TxBD[I] and TCT[IMK] = 1. This interrupt has an associated channel code.

RXB

Rx buffer. RXB is set when an Rx buffer interrupt is issued. This interrupt is enabled when

both RxBD[I] and RCT[RXBM] = 1. This interrupt has an associated channel code.

0x02

—

Channel code specifies the channel associated with this interrupt.

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