MPC8280 datasheet(1036/1386 Pages) FREESCALE

1036 / 1386 page

ATM Controller and AAL0, AAL1, and AAL5

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

31-76

Freescale Semiconductor

31.10.5.12 AAL0 TxBDs

Figure 31-52 shows AAL0 TxBDs. Note that the data length field is calculated internally as 52 bytes, plus

the extra header length (defined in FPSMR[TEHS]) when in UDC mode.

Table 31-40 describes AAL0 TxBD fields.

Continuous mode

0 Normal operation.

1 The CP does not clear the ready bit after this BD is closed, allowing the associated

buffer to be retransmitted automatically when the CP next accesses this BD.

7–11

—

Reserved, should be cleared.

0x02

—

The number of octets the ATM controller should transmit from this BD’s buffer. It is not

modified by the CP. The value of DL should be greater than zero.

0x04

—

TXDBPTR Tx data buffer pointer. Points to the address of the associated buffer. The buffer may

reside in either internal or external memory. This value is not modified by the CP.

234567

Offset + 0x00

—

OAM

—

Offset + 0x02

—

Offset + 0x04

Tx Data Buffer Pointer (TXDBPTR)

Offset + 0x06

Figure 31-52. AAL0 TxBDs

Table 31-40. AAL0 TxBD Field Descriptions

Offset

Bits

Name

Description

0x00

Ready

0 The buffer is not ready for transmission. The user can manipulate this BD or its buffer.

The CP clears R after the buffer has been sent or after an error occurs.

1 The buffer that the user prepared for transmission has not been sent or is being sent.

No fields of this BD may be written by the user once R is set.

—

Reserved, should be cleared.

Wrap (final BD in table)

0 Not the last BD in the TxBD table.

1 Last BD in the TxBD table. After this buffer is used, the CP sends outgoing data from

the first BD in the table (the BD pointed to by the channel’s TCT[TBD_BASE]). The

number of TxBDs in this table is determined by the W bit. The current table is

constrained to 64 Kbytes.

Interrupt

0 No interrupt is generated after this buffer has been serviced.

1 A Tx buffer event is sent to the interrupt queue after this buffer is serviced.

FCCE[GINT

x] is set when the INT_CNT counter reaches the global interrupt

threshold.

Table 31-39. AAL1 TxBD Field Descriptions

Offset

Bits

Name

Description

MPC8280 Datasheet(PDF) 1036 Page - Freescale Semiconductor, Inc

MPC8280 Datasheet(HTML) 1036 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL