MPC8280 datasheet(1035/1386 Pages) FREESCALE

1035 / 1386 page

ATM Controller and AAL0, AAL1, and AAL5

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

31-75

31.10.5.11 AAL1 TxBDs

Figure 31-51 shows the AAL1 TxBD.

Table 31-39 describes AAL1 TxBD fields.

CNG

The ATM cell header CNG bit of the cells associated with the current frame are ORed

with this field. This field is valid only in the first BD of the frame.

12–15

—

Reserved, should be cleared.

0x02

—

The number of octets the ATM controller should transmit from this BD’s buffer. It is not

modified by the CP. The value of DL should be greater than zero.

0x04

—

TXDBPTR Tx data buffer pointer. Points to the address of the associated buffer, which may or may

not be 8-byte-aligned. The buffer may reside in either internal or external memory. This

value is not modified by the CP.

23456789

Offset + 0x00

—

Offset + 0x02

Data Length (DL)

Offset + 0x04

Tx Data Buffer Pointer (TXDBPTR)

Offset + 0x06

Figure 31-51. AAL1 TxBD

Table 31-39. AAL1 TxBD Field Descriptions

Offset

Bits

Name

Description

0x00

Ready

0 The buffer associated with this BD is not ready for transmission. The user is free to

manipulate this BD or its associated buffer. The CP clears this bit after the buffer has

been sent or after an error condition is encountered.

1 The buffer prepared for transmission by the user has not been sent or is being sent.

No fields of this BD may be written by the user once R is set.

—

Reserved, should be cleared.

Wrap (final BD in table)

0 Not the last BD in the TxBD table.

1 Last BD in the TxBD table. After this buffer is used, the CP sends outgoing data from

the first BD in the table (the BD pointed to by the channel’s TCT[TBD_BASE]). The

number of TxBDs in this table is determined only by the W bit. The current table cannot

exceed 64 Kbytes.

Interrupt

0 No interrupt is generated after this buffer has been serviced.

1 A Tx buffer event is sent to the interrupt queue after this buffer is serviced.

FCCE[GINT

x] is set when the INT_CNT counter reaches the global interrupt

threshold.

4–5

—

Reserved, should be cleared.

Table 31-38. AAL5 TxBD Field Descriptions (continued)

Offset

Bits

Name

Description

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