MPC8280 datasheet(1032/1386 Pages) FREESCALE

1032 / 1386 page

ATM Controller and AAL0, AAL1, and AAL5

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

31-72

Freescale Semiconductor

31.10.5.6 AAL0 RxBD

Figure 31-48 shows the AAL0 RxBD.

Table 31-37 describes AAL0 RxBD fields.

Continuous mode

0 Normal operation.

1 The empty bit (RxBD[E]) is not cleared by the CP after this BD is closed, allowing the

associated buffer to be overwritten automatically when the CP next accesses this BD.

7–15

—

Reserved, should be cleared.

0x02

—

Data length. The number of octets the CP writes into the buffer once its BD is closed.

0x04

—

RXDBPTR Rx data buffer pointer. Points to the first location of the associated buffer; may reside in

either internal or external memory. It is recommended that the pointer be burst-aligned.

234567

Offset + 0x00

—

CRE OAM

—

Offset + 0x02

Data Length (DL)/Channel Code (CC)

Offset + 0x04

Rx Data Buffer Pointer (RXDBPTR)

Offset + 0x06

Figure 31-48. AAL0 RxBD

Table 31-37. AAL0 RxBD Field Descriptions

Offset

Bits

Name

Description

0x00

Empty

0 The buffer associated with this RxBD is filled with received data, or data reception was

aborted due to an error. The core can examine or write to any fields of this RxBD. The

CP does not use this BD again while E remains zero.

1 The Rx buffer is empty or reception is in progress. This RxBD and its associated

receive buffer are owned by the CP. Once E is set, the core should not write any fields

of this RxBD.

—

Reserved, should be cleared.

Wrap (final BD in table)

0 This is not the last BD in the RxBD table of the current channel.

1 This is the last BD in the RxBD table of the current channel. After this buffer has been

used, the CP will receive incoming data into the first BD in the table. The number of

RxBDs in this table is programmable and is determined only by the W bit. The current

table cannot exceed 64 Kbytes.

Interrupt

0 No interrupt is generated after this buffer has been used.

1 An Rx buffer event is sent to the interrupt queue after the ATM controller uses this

buffer. FCCE[GINT

x] is set when the INT_CNT reaches the global interrupt threshold.

4–5

—

Reserved, should be cleared.

Table 31-36. AAL1 RxBD Field Descriptions (continued)

Offset

Bits

Name

Description

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