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MPC8280 Datasheet(PDF) 1031 Page - Freescale Semiconductor, Inc

Part # MPC8280
Description  PowerQUICC??II Family Reference Manual
PDF  1386 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8280 Datasheet(HTML) 1031 Page - Freescale Semiconductor, Inc

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ATM Controller and AAL0, AAL1, and AAL5
MPC8280 PowerQUICC II Family Reference Manual, Rev. 1
Freescale Semiconductor
31-71
31.10.5.5 AAL1 RxBD
Figure 31-47 shows the AAL1 RxBD.
Table 31-36 describes AAL1 RxBD fields.
0x02
—
DL
Data length. The number of octets written by the CP into this BD’s buffer. It is written
by the CP once the BD is closed. In the last BD of a frame, DL contains the total frame
length.
0x04
RXDBPTR Rx data buffer pointer. Points to the first location of the associated buffer; may reside
in internal or external memory. It is recommended that the pointer be burst-aligned.
0
123456789
10
11
12
13
14
15
Offset + 0x00
E
—
WI
SNE
—
CM
—
Offset + 0x02
Data Length
Offset + 0x04
Rx Data Buffer Pointer
Offset + 0x06
Figure 31-47. AAL1 RxBD
Table 31-36. AAL1 RxBD Field Descriptions
Offset
Bits
Name
Description
0x00
0
E
Empty
0 The buffer associated with this RxBD is filled with received data or data reception was
aborted due to an error. The core can read or write any fields of this RxBD. The CP
cannot use this BD again while E = 0.
1 The buffer is not full. This RxBD and its associated receive buffer are owned by the
CP. Once E is set, the core should not write any fields of this RxBD.
1
—
Reserved, should be cleared.
2
W
Wrap (final BD in table)
0 This is not the last BD in the RxBD table of the current channel.
1 This is the last BD in the RxBD table of this current channel. After this buffer is used,
the CP receives incoming data into the first BD in the table. The number of RxBDs in
this table is programmable and is determined only by the W bit. The current table
overall space is constrained to 64 Kbytes.
3
I
Interrupt
0 No interrupt is generated after this buffer has been used.
1 An Rx buffer event is sent to the interrupt queue after the ATM controller uses this
buffer. FCCE[GINT
x] is set when the INT_CNT reaches the global interrupt threshold.
4
SNE
Sequence number error. SNE is set when a sequence number error is detected in the
current AAL1 CES buffer.
5
—
Reserved, should be cleared.
Table 31-35. AAL5 RxBD Field Descriptions (continued)
Offset
Bits
Name
Description



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