MPC8280 datasheet(1049/1386 Pages) FREESCALE

1049 / 1386 page

ATM Controller and AAL0, AAL1, and AAL5

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

31-89

Table 31-48 describes FCCE fields.

31.14 ATM Transmit Command

The CPM command set includes an ATM TRANSMIT that can be sent to the CP command register (CPCR),

described in Section 14.4.1.

The ATM TRANSMIT command (CPCR[opcode] = 0b1010, CPCR[SBC[code]] = 0b01110,

CPCR[SBC[page]] = 0b00100 or 0b00101 (FCC1 or FCC2), CPCR[MCN] = 0b0000_1010) turns a

passive channel into an active channel by inserting it into the APC scheduling table. Note that an ATM

TRANSMIT

command should be issued only after the channel’s TCT is completely initialized and the

channel has BDs ready to transmit. Note also that CPCR[SBC[code]] = 0b01110 and not FCC1 or FCC2

code.

Before issuing the command, the user should initialize COMM_INFO fields in the parameter RAM as

described in Figure 31-61.

Table 31-48. FCCE/FCCM Field Descriptions

Bits

Name

Description

0–4

—

Reserved, should be cleared.

TIRU

Transmit internal rate underrun. A cumulative lag of seven cells has formed between the

programmable rate and the actual rate for a specific Phy. A transmit internal rate counter expired

and a cell was not sent, either because of slow CPM performance or slow PHY performance. TIRU

may be set only when using transmit internal rate mode; see Section 31.15.1.1, “FCC Transmit

Internal Rate Register (FTIRRx).”

GRLI

Global red-line interrupt. GRLI is set when a free buffer pool’s RLI flag is set. The RLI flag is also set

in the free buffer pool’s parameter table.

GBPB

Global buffer pool busy interrupt. GBPB is set when a free buffer pool’s BUSY flag is set. The BUSY

flag is also set in the free buffer pool’s parameter table.

8–11

GINT

x Global interrupt. Set when the number of events sent to the corresponding interrupt queue reaches

the corresponding event threshold. See Section 31.11, “ATM Exceptions.”

12–15

INTO

x Interrupt queue overflow. Set when an overflow condition occurs in the corresponding interrupt

queue. This occurs when the CP attempts to overwrite a valid interrupt entry. See Section 31.11.1,

“Interrupt Queues.”

16–31

—

Reserved, should be cleared.

Offset

0x86

—

CTB

PHY#

ACT

PRI

0x88

Channel Code (CC)

0x8A

Figure 31-61. COMM_INFO Field

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