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MPC8280 Datasheet(PDF) 1052 Page - Freescale Semiconductor, Inc

Part # MPC8280
Description  PowerQUICC??II Family Reference Manual
PDF  1386 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8280 Datasheet(HTML) 1052 Page - Freescale Semiconductor, Inc

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ATM Controller and AAL0, AAL1, and AAL5
MPC8280 PowerQUICC II Family Reference Manual, Rev. 1
31-92
Freescale Semiconductor
Table 31-50 describes FTIRRx fields.
Figure 31-63 shows how transmit clocks are determined.
.
Figure 31-63. FCC Transmit Internal Rate Clocking
31.15.1.2 Example
Suppose the MPC8280 is connected to four 155 Mbps PHY devices and the maximum transmission rate
is 155 Mbps for the first PHY and 10 Mbps for the rest of the PHYs. The BRG CLK should be set
according to the highest rate. If the CPM clock is 133 MHz and the BRG CLK is 66 MHz, the BRG should
be programmed to divide the CPM clock by 181 to generate cell transmit requests every 362 system clocks:
01
7
Field
TRM
Initial Value
Reset
0000_0000
R/W
R/W
Address
GFEMR[TIREM=0]
FCC1: 0x1131C (FTIRR1_PHY0),
FCC1: 0x1131D (FTIRR1_PHY1),
FCC1: 0x1131E (FTIRR1_PHY2),
FCC1: 0x1131F (FTIRR1_PHY3),
FCC2: 0x1133C (FTIRR2_PHY0),
FCC2: 0x1133D (FTIRR2_PHY1),
FCC2: 0x1133E (FTIRR2_PHY2),
FCC2: 0x1133F (FTIRR2_PHY3).
GFEMR[TIREM=1]
FCC1: 0x1131C (FTIRR1_GRP0),
FCC1: 0x1131D (FTIRR1_GRP1),
FCC1: 0x1131E (FTIRR1_GRP2),
FCC1: 0x1131F (FTIRR1_GRP3),
FCC2: 0x1133C (FTIRR2_GRP0),
FCC2: 0x1133D (FTIRR2_GRP1),
FCC2: 0x1133E (FTIRR2_GRP2),
FCC2: 0x1133F (FTIRR2_GRP3).
Figure 31-62. FCC Transmit Internal Rate Register (FTIRR)
Table 31-50. FTIRR
x Field Descriptions
Bit
Name
Description
0TRM
(TIREM=0)
PHY transmit mode
0 External rate mode.
1 Internal rate mode.
TRM
(TIREM=1)
Group transmit mode
0
Group rate timer [x] disabled.
1 Internal rate timer for Group[x] is enabled and division factor is set by Initial Value field.
1–7
Initial Value
The initial value of the internal rate timer. A value of 0x7F produces the minimum clock rate
(BRG CLK divided by 128); 0x00 produces the maximum clock rate (BRG CLK divided by 1).
BRG CLK
PHY#0 Int rate timer
PHY#1 Int rate timer
PHY#2 Int rate timer
PHY#3 Int rate timer
PHY# 0 or GRP#0 Tx Rate
PHY# 1 or GRP#1Tx Rate
PHY# 2 or GRP#2 Tx Rate
PHY# 3 or GRP#3 Tx Rate



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