MPC8280 datasheet(1054/1386 Pages) FREESCALE

1054 / 1386 page

ATM Controller and AAL0, AAL1, and AAL5

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

31-94

Freescale Semiconductor

Table 31-51 describes FIRPERx fields.

31.15.1.5 FCC Internal Rate Event Registers (FIRER

Transmit internal rate underrun (TIRU) errors are reported for any PHY that has a transmission deficiency

of 8 cells. Under this condition and in internal rate mode only, FCCE[TIRU] is set, and if the corresponding

bit in the FCC mask register (FCCM[TIRU]) is set, an interrupt is generated. If TIREM = 1, the TIRU

status per PHY can be read at any time in the FCC internal rate event register (FIRER). Once

FIRER[TIRUy] error status is set, it can be cleared only by writing 1 to it. To prevent an underrun PHY

from continuously reporting errors, it can be disabled by FIRPER. The sequence of disabling a PHY is as

follows:

•

Disable PHY y by clearing FIRPER[y]

•

Clear event FIRER[y] by writing 1 to it

•

Clear event FCCE[TIRU] by writing 1 to it

012

345678

Field

PE0

PE1

PE2

PE3

PE4

PE5

PE6

PE7

PE8

PE9

PE10 PE11 PE12 PE13 PE14 PE15

Reset

0000_0000_0000_0000

R/W

Addr

0x11380 (FIRPER1), 0x113A0 (FIRPER2)

Field PE16 PE17 PE18 PE19 PE20 PE21 PE22 PE23 PE24 PE25 PE26 PE27 PE28 PE29 PE30

—

Reset

0000_0000_0000_0000

R/W

Addr

0x11382 (FIRPER1), 0x113A2 (FIRPER2)

Figure 31-64. FCC Transmit Internal Rate Port Enable Register (FIRPER

Table 31-51. FIRPER

x Field Descriptions (TIREM=1)

Bit

Name

Description

0–15

PEy

Port enable

0 Transmit internal rate for PHY address y is disabled. TxClav from this PHY is masked.

1 Transmit Internal rate for PHY address y is enabled. The rate assigned for PHY y is selected by

(FIRSRx_HI, FIRSRx_LO)”).

16–30

PEy

Port enable.

0 Transmit internal rate for PHY address y is disabled. TxClav from this PHY is masked.

1 Transmit Internal rate for PHY address y is enabled. The rate assigned for PHY y is selected by

(FIRSRx_HI, FIRSRx_LO)”).

—

Reserved, should be cleared.

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