MPC8280 datasheet(1058/1386 Pages) FREESCALE

1058 / 1386 page

ATM Controller and AAL0, AAL1, and AAL5

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

31-98

Freescale Semiconductor

Figure 31-69. AAL1 CES SRTS Clock Recovery Using External Logic

On every eighth cell, the MPC8280 writes a new SRTS code to the external logic using the bus selected in

RCT[BIB]. The CP writes the SRTS code using a DMA write cycle of 1-byte data size. Each AAL1 CES

channel can be programmed to select one of 16 addresses available for writing the SRTS result. The SRTS

code is written to the least-significant nibble of that address (SRTS[0]=lsb, SRTS[3]=msb). The SRTS is

synchronized with the sequence count cycle—SRTS[3] is read from the cell with SN = 1 and SRTS[0] is

read from the cell with SN = 7. The SRTS PLL makes periodic clock adjustments based on the difference

between a locally generated SRTS and a remotely generated SRTS retrieved every eight received cells.

31.17 Configuring the ATM Controller for Maximum CPM Performance

The following sections recommend ATM controller configurations to maximize CPM performance.

31.17.1 Using Transmit Internal Rate Mode

When the total transmit rate is less than the PHY rate, use the transmit internal rate mode and configure

the internal rate clock to the maximum bit rate required. (See 31.2.1.5, “Transmit External Rate and

Internal Rate Modes.”) The PHY then automatically fills the unused bandwidth with idle cells, not the

ATM controller. If the internal rate mode is not used, CPM performance is consumed generating the idle

cell payload and using the scheduling algorithm to fill the unused bandwidth at the higher PHY rate.

For example, suppose a system uses a 155.52-Mbps OC-3 device as PHY0, but the maximum required data

rate is only 100 Mbps. In transmit internal rate mode, the user can configure the internal rate mechanism

to clock the ATM transmitter at a cell rate of 100 Mbps. If the system clock is 133 MHz, program a BRG

to divide the system clock by 563 to generate a transmit cell request every 563 CPM clocks:

p = 4 bit

1/64

155.52 MHz

2.43 MHz (E1/T1)

Latch

Counter

divided by N

(N=3008 bits = 8 SAR PDU)

SRTS

External SRTS Logic

SRTS Diff

VCO

SN=1

SN=3

SN=5

SN=7

DMA writes new SRTS code

Latch

counter

133MHz

()

100Mbps

-----------------------------------------------------

563

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