MPC8280 datasheet(1053/1386 Pages) FREESCALE

1053 / 1386 page

ATM Controller and AAL0, AAL1, and AAL5

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

31-93

For the 155 Mbps PHY, the FTIRR divider should be programmed to zero (the BRG CLK is divided by

one); for the rest of the 10 Mbps PHYs, the FTIRR divider should be programmed to 14 (the BRG CLK

is divided by 15).

See also Section 31.17.1, “Using Transmit Internal Rate Mode.”

31.15.1.3 Internal Rate Programming Model

The programming sequence in TIREM = 0 mode is as follows:

1. Clear GFEMRx[TIREM]

2. Program FTIRRx

The programming sequence in TIREM = 1 mode is as follows:

1. Clear FTIRRx[TRM]

2. Set GFEMRx[TIREM]

3. Program FIRSRx_HI and FIRSRx_LO

4. Program FTIRRx

5. Program FIRPERx

If FTIRRx are set to generate same order of magnitude rates, setting round robin polling mode is more

adequate than fixed priority mode. To reduce the risk of transmit underrun if there are a few PHYs with

high internal rate and a number of PHYs with a low internal rate, the fast PHYs should be assigned

consecutive addresses starting at 0 and fixed priority mode should be chosen.

31.15.1.4 FCC Transmit Internal Rate Port Enable Registers (FIRPERx)

This register enables internal rate transmission for PHYs[0-30]. It is valid only if GFEMR[TIREM] = 1.

If a PHY is not enabled in FIRPER, all TxClav indications from that PHY will be masked. The user should

configure FIRPER according to the PHY addresses which are being used on the UTOPIA bus and should

not enable PHYs with addresses larger then the last PHY address set by FPSMR[Last PHY]. PHYs can be

enabled or disabled at any time—for example, if a TIRU event has occurred.

66MHz

()

155.52Mbps

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MPC8280 Datasheet(PDF) 1053 Page - Freescale Semiconductor, Inc