MPC8280 datasheet(1050/1386 Pages) FREESCALE

1050 / 1386 page

ATM Controller and AAL0, AAL1, and AAL5

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

31-90

Freescale Semiconductor

Table 31-49 describes COMM_INFO fields.

31.15 Transmission Rate Modes—External, Internal, and Expanded

Internal

The ATM controller supports the following three rate modes:

•

External rate mode—The total transmission rate is determined by the PHY transmission rate. The

FCC sends cells to keep the PHY FIFOs full; the FCC inserts idle/unassign cells to maintain the

transmission rate.

•

Internal rate mode—The total transmission rate is determined by the FCC internal rate timers. In

this mode, the FCC does not insert idle/unassign cells. The internal rate mechanism is supported

for the first four PHY devices (PHY address 0-3). Each PHY has its own FTIRR, described in

Section 31.15.1.1, “FCC Transmit Internal Rate Register (FTIRRx).” The FTIRR includes the

initial value of the internal rate timer. A cell transmit request is sent when an internal rate timer

expires. When using internal rate mode, the user assigns one of the baud-rate generators (BRGs)

to clock the four internal rate timers.

•

Internal rate expanded mode—The total transmission rate is determined by the FCC internal rate

timers and by the assignment of rate per PHY. In this mode, the FCC does not insert idle/unassign

cells. The internal rate expanded mode differs from the internal rate mode in that the internal rate

mechanism is extended for 31 PHY devices (PHY addresses 0-30) and there cannot be a mix of

external and internal rate PHYs. Expanded internal rate is configured by registers GFEMRx,

FIRPERx, FIRSRx_HI, FIRSRx_LO, and by FTIRRx. Another feature of internal rate expanded

mode is an indication of transmit underrun error status per PHY. When using internal rate expanded

mode, the user assigns one of the baud-rate generators (BRGs) to clock the four internal rate timers,

and any timer can trigger any PHY.

Table 31-49. COMM_INFO Field Descriptions

Offset

Bits

Name

Description

0x86

0–4

—

Reserved, should be cleared.

CTB

Connection tables bus. Used for external channels only

0 External connection tables reside on the 60x bus.

1 External connection tables reside on the local bus.

6–10

PHY#

PHY number. In single PHY mode this field should be cleared In multiple PHY mode this

field is an index to the APC parameter table associated with this channel.

11–12

ACT

ATM channel type

00 Other channel

01 VBR channel

1x Reserved

13-15

PRI

APC priority level.

000 Highest priority (APC_LEVEL1)

111 Lowest priority (APC_LEVEL8).

0x88

0-15

Channel code. The channel code associated with the current channel.

0x8A

0-15

Burst tolerance. For use by VBR channels only (ACT field is 0b01). Specifies the initial

burst tolerance (GCRA burst credit) of the current VC.

MPC8280 Datasheet(PDF) 1050 Page - Freescale Semiconductor, Inc

MPC8280 Datasheet(HTML) 1050 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL