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MPC8280 Datasheet(PDF) 1097 Page - Freescale Semiconductor, Inc

Part # MPC8280
Description  PowerQUICC??II Family Reference Manual
PDF  1386 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8280 Datasheet(HTML) 1097 Page - Freescale Semiconductor, Inc

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ATM AAL1 Circuit Emulation Service
MPC8280 PowerQUICC II Family Reference Manual, Rev. 1
Freescale Semiconductor
32-37
current BD is not ready, the CP polls the ready bit at the channel rate unless TCT[AVCF] = 1, in which
case the CP removes the channel from the APC and clears TCT[VCON]. The core must issue a new atm
transmit command to restart transmission.
Note that when the ATM transmitter is in CES mode, the buffer-not-ready state is ignored by the ATM
controller; see Section 32.4.1.2, “TDM-to-ATM.”
Figure 32-26. Transmit Buffers and BD Table Example
32.11.2 Receive Buffer Operation
The user prepares a table of BDs pointing to the receive buffers. The address of the first BD is put in the
channel’s RCT[RBD_BASE]. When an ATM cell arrives, the CP opens the first BD in the table and starts
filling its associated buffer with received data. When the current buffer is full, the CP increments
RBD_OFFSET, which is the offset to the current BD from RBD_BASE, and reads the next BD in the table.
If the BD is empty (RxBD[E] = 1), the CP continues receiving. If the BD is not empty, a busy condition
has occurred and the ATM receiver optionally issues an interrupt to the event queue.
Note that when the ATM receiver is in CES mode, the buffer-not-ready (busy) state is handled by an
automatic slip control mechanism; see Section 32.5, “ATM-to-TDM Adaptive Slip Control.”
BD memory space
TBD_Base
Tx BD table
of ch 1
Tx BD table
of ch 4
TBD_Offset
TBD_Base
TBD_Offset
Pointers
TxBD 1
TxBD 2
TxBD 3
TxBD 4
TxBD 5
TxBD 6
TxBD 7
TxBD 8
TxBD 9
TxBD 1
TxBD 2
TxBD 3
TxBD 4
TxBD 5
TxBD 6
Tx buffer 3 of
channel 1
Tx buffer 4 of
channel 1
Tx buffer 1 of
channel 4
Tx buffer 2 of
channel 4
Tx buffer 3 of
channel 4
Tx buffer 2 of
channel 1
Tx buffer 8 of
channel 4
•
•
•
•
•
•
Tx buffer 1 of
channel 1
Data memory space
from ch 1
entry of
TCT
Pointers
from ch 4
entry of
TCT



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