MPC8280 datasheet(1099/1386 Pages) FREESCALE

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ATM AAL1 Circuit Emulation Service

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

32-39

32.12.1 AAL1 CES RxBD

Figure 32-28 shows the AAL1 CES RxBD.

Table 32-11 describes AAL1 CES RxBD fields.

012

345

678

Offset + 0x00

—

EOSF

—

Offset + 0x02

Data Length

Offset + 0x06

Rx Data Buffer Pointer

Offset + 0x08

Figure 32-28. AAL1 CES RxBD

Table 32-11. AAL1 CES RxBD Field Descriptions

Offset

Bits

Name

Description

0x00

Empty.

0 The buffer associated with this RxBD is filled with received data or data reception was

aborted due to an error. The core can read or write any fields of this RxBD. The CP

cannot use this BD again while E = 0.

1 The buffer is not full. This RxBD and its associated receive buffer are owned by the CP.

Once E is set, the core should not write any fields of this RxBD.

1—

—

Wrap (final BD in table)

0 This is not the last BD in the RxBD table of the current channel.

1 This is the last BD in the RxBD table of this current channel. After this buffer is used, the

CP receives incoming data into the first BD in the table. The number of RxBDs in this

table is programmable and is determined only by the W bit. The current table overall

space is constrained to 64 Kbytes.

Interrupt

0 No interrupt is generated after this buffer has been used.

1 An Rx buffer event is sent to the interrupt queue after the ATM controller uses this buffer.

FCCE[GINT

x] is set when the INT_CNT reaches the global interrupt threshold.

4-5

—

Continuous mode

0 Normal operation.

1 The empty bit (RxBD[E]) is not cleared by the CP after this BD is closed, allowing the

associated buffer to be overwritten automatically when the CP next accesses this BD.

7-8

—

EOSF

End of super frame. CES mode (RCT[CESM=1]) only.

0 No signaling information should be inserted after closing this buffer.

1 When closing this buffer, the ATM receiver unpacks the CAS information from the

incoming AAL1 cells and stores it in the internal CAS block.

Note that this bit should be set by the user at the end of each super-frame in the common

(MCC, ATM) BD table. See Section 32.4.6, “Channel Associated Signaling (CAS)

Support.”

10-15

—

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