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MPC8280 Datasheet(PDF) 1103 Page - Freescale Semiconductor, Inc |
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MPC8280 Datasheet(HTML) 1103 Page - Freescale Semiconductor, Inc |
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1103 / 1386 page ![]() ATM AAL1 Circuit Emulation Service MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 32-43 32.15 Internal AAL1 CES Statistics Tables An AAL1 CES statistics table, shown in Table 32-14, resides in the dual-port RAM and holds AAL1 CES statistics on a per-VC basis. AAL1_Int_STATT_BASE points to the base address of these tables. Each AAL1 channel has its own table with a starting address given by AAL1_Int_STATT_BASE + ATM_CHANNEL# × 8. 0 15 Offset + 0x00 0x0000 Offset + 0x02 0x0007 Offset + 0x04 0x000D Offset + 0x06 0x000A Offset + 0x08 0x000E Offset + 0x0A 0x0009 Offset + 0x0C 0x0003 Offset + 0x0E 0x0004 Offset + 0x10 0x000B Offset + 0x12 0x000C Offset + 0x14 0x0006 Offset + 0x16 0x0001 Offset + 0x18 0x0005 Offset + 0x1A 0x0002 Offset + 0x1C 0x0008 Offset + 0x1E 0x000F Figure 32-31. AAL1 Sequence Number (SN) Protection Table Table 32-14. AAL1 CES DPR Statistics Table Offset Name Width Description 0x00 Rx_AAL1_VALID Hword 16-bit cyclic counter. Counts the total received AAL1 cells delivered to the receive buffers. This counter includes the tag cells (with SCE, SNE). 0x02 Rx_AAL1_BOV Hword 16-bit cyclic counter. Counts the number of ATM buffer-pre overrun events i.e the ATM write pointer reaches the ATM_STOP threshold.See Section 32.5, “ATM-to-TDM Adaptive Slip Control.” 0x04 Tx_AAL1_VALID Hword 16-bit cyclic counter. Counts the transmitted AAL1 cells. 0x06 Tx_AAL1_BUN Hword 16-bit cyclic counter. Counts the number of ATM buffer underrun events. See Section 32.4.1.2, “TDM-to-ATM.” |
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