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MPC8280 Datasheet(PDF) 1100 Page - Freescale Semiconductor, Inc

Part # MPC8280
Description  PowerQUICC??II Family Reference Manual
PDF  1386 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8280 Datasheet(HTML) 1100 Page - Freescale Semiconductor, Inc

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ATM AAL1 Circuit Emulation Service
MPC8280 PowerQUICC II Family Reference Manual, Rev. 1
32-40
Freescale Semiconductor
32.12.2 AAL1 CES TxBDs
Figure 32-29 shows the AAL1 CES TxBD.
Table 32-12 describes AAL1 CES TxBD fields.
0x02
—
DL
Data length. The number of octets the CP writes into the buffer once its BD is closed.
0x04
—
RXDBPTR Rx data buffer pointer. Points to the first location of the associated buffer; may reside in
either internal or external memory. This pointer must be burst-aligned.
012
34
56
7
8
9
10
15
Offset + 0x00
R
—
W
I
—
CM
—
EOSF
—
Offset + 0x02
Data Length (DL)
Offset + 0x04
Tx Data Buffer Pointer (TXDBPTR)
Offset + 0x06
Figure 32-29. AAL1 CES TxBD
Table 32-12. AAL1 CES TxBD Field Descriptions
Offset
Bits
Name
Description
0x00
0
R
Ready
0 The buffer associated with this BD is not ready for transmission. The user is free to
manipulate this BD or its associated buffer. The CP clears this bit after the buffer has
been sent or after an error condition is encountered.
1 The buffer prepared for transmission by the user has not been sent or is being sent.
No fields of this BD may be written by the user once R is set.
1—
—
2
W
Wrap (final BD in table)
0 Not the last BD in the TxBD table.
1 Last BD in the TxBD table. After this buffer is used, the CP sends outgoing data from
the first BD in the table (the BD pointed to by the channel’s TCT[TBD_BASE]). The
number of TxBDs in this table is determined only by the W bit. The current table
cannot exceed 64 Kbytes.
3
I
Interrupt
0 No interrupt is generated after this buffer has been serviced.
1 A Tx buffer event is sent to the interrupt queue after this buffer is serviced.
FCCE[GINT
x] is set when the INT_CNT counter reaches the global interrupt
threshold.
4–5
—
—
6
CM
Continuous mode
0 Normal operation.
1 The CP does not clear the ready bit after this BD is closed, allowing the associated
buffer to be retransmitted automatically when the CP next accesses this BD.
7–8
—
—
Table 32-11. AAL1 CES RxBD Field Descriptions
Offset
Bits
Name
Description



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