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MPC8280 Datasheet(PDF) 1142 Page - Freescale Semiconductor, Inc |
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MPC8280 Datasheet(HTML) 1142 Page - Freescale Semiconductor, Inc |
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1142 / 1386 page  ATM AAL2 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 33-36 Freescale Semiconductor 0x98 AAL1_SNPT_BASE Hword AAL1 SN protection look up table base address. (AAL1 only.) The 32-byte table resides in dual-port RAM and must be initialized by the user (See Section 31.10.6, “AAL1 Sequence Number (SN) Protection Table”). 0x9A — Hword Reserved. Should be cleared during initialization. 0x9C SRTS_BASE Word External SRTS logic base address. (AAL1 only.) Should be 16-byte aligned. 0xA0 IDLE/UNASSIGN_BASE Hword Idle/unassign cell base address. Points to dual-port RAM area contains idle/unassign cell template (little-endian format). Should be 64-byte aligned. User-defined. The ATM header should be 0x0000_0000 or 0x0100_0000 (CLP=1). 0xA2 IDLE/UNASSIGN_SIZE Hword Idle/Unassign cell size. 52 in regular mode. 53–64 in UDC mode. 0xA4 EPAYLOAD Word Reserved payload. Initialize to 0x6A6A6A6A. 0xA8 Trm Word (ABR only) The upper bound on the time between F-RM cells for an active source. TM 4.0 defines the Trm period as 100 msec. The Trm value is defined by the system clock and the time stamp timer prescaler (See RTSCR). For time stamp prescalar of 1µs, Trm should be set to 100 ms/1µs = 100,000. 0xAC Nrm Hword (ABR only) Controls the maximum cells the source may send for each F-RM cell. Set to 32 cells. 0xAE Mrm Hword (ABR only) Controls the bandwidth between F-RM, B-RM and user data cell. Set to 2 cells. 0xB0 TCR Hword (ABR only) Tag cell rate. The minimum cell rate allowed for all ABR channels. An ABR channel whose ACR is less than TCR sends only out-of-rate F-RM cells at TCR. Should be set to 10 cells/sec as defined in the TM 4.0. Uses the ATMF TM 4.0 floating-point format. Note that the APC minimum cell rate should be at least TCR. 0xB2 ABR_RX_TCTE Hword (ABR only) Points to total of 16 bytes reserved dual-port RAM area used by the CP. Should be 16-byte aligned. User-defined. 0xB4 RxQD_Base_Ext Word Points to the base address of the external RxQD table. The actual address of the first RxQD in the table is RxQD_Base_Ext + 512*4. User-defined. 0xB8 RX_UDC_Base Word Valid only for AAL2 VCs. Points to the base of the RX UDC header table that contains the UDC headers of the AAL2 VCs. The pointer to a VC UDC header is: RX_UDC_Base + 16*CH# (where CH# is the ATM channel number) 0xBC TX_UDC_Base Word Valid only for AAL2 VCs. Points to the base of the TX UDC header table that contains the UDC headers of the AAL2 VCs. The pointer to a VC UDC header is: TX_UDC_Base + 16*CH# (where CH# is the ATM channel number) 0xC0– 0xDF — — Reserved. Should be cleared during initialization. Table 33-13. AAL2 Parameter RAM (continued) Offset Name Width Description |
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