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MPC8280 Datasheet(PDF) 1139 Page - Freescale Semiconductor, Inc

Part # MPC8280
Description  PowerQUICC??II Family Reference Manual
PDF  1386 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8280 Datasheet(HTML) 1139 Page - Freescale Semiconductor, Inc

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ATM AAL2
MPC8280 PowerQUICC II Family Reference Manual, Rev. 1
Freescale Semiconductor
33-33
Table 33-12 describes the SSSAR RxBD fields.
Table 33-12. SSSAR RxBD Field Descriptions
Offset
Bits
Name1
Description
0x00
0
E
Empty
0 The buffer associated with this RxBD is full or data reception was aborted due to an
error. The core can read or write any fields of this RxBD. The CP does not use this
BD again while E remains zero.
1 The buffer associated with this RxBD is empty or reception is in progress. This RxBD
and its receive buffer are controlled by the CP. Once E is set, the core should not
write any fields of this RxBD.
1
CM
Continuous mode
0 Normal operation
1 The CP does not clear E after this BD is closed, allowing the associated buffer to
be reused automatically when the CP next accesses this BD. However, the E bit is
cleared if an error occurs while receiving, regardless of the CM bit setting.
2
W
Wrap (final BD in the table)
0 This is not the last BD in the RxBD table of the current channel.
1 This is the last BD in the RxBD table of this current channel. After this buffer has
been used, the CP receives incoming data for this channel into the first BD in the
table. The number of RxBDs in this table is programmable and is determined only
by the W bit. The current table cannot exceed 64 Kbytes.
3
I
Interrupt
0 No interrupt is generated after this buffer has been serviced.
1 An Rx buffer event is sent (provided that RxQD[RBM] is set) to the interrupt queue
after this buffer is serviced. The GHIN/GLIN bit in the event register is set when the
INT_CNT counter reaches terminal count.
4
L
Last. Set by the CP.
0 This is not the last buffer of the SSSAR SDU.
1 This is the last buffer of the SSSAR SDU.
5–6
RxError
Rx error occurred
00 No Rx error occurred
01 TE—Ras_Timer expired. The Ras Timer expired before this buffer could be
completed. The SSSAR SDU stored in this buffer is not completed.2
10 US—Uncompleted SDU. A receive error caused a packet belonging to this
SSSAR SDU to be lost. The receiver discarded the rest of this SSSAR SDU.
11 OS—Oversized. The size of the SSSAR SDU has exceeded the
Max_SSSAR_SDU_Size parameter. The rest of the SDU was discarded.
7–10
—
Reserved, should be cleared during initialization.
11–15
UUI
Contains the UUI of the last packet in the received SDU. Valid only where the L bit is
set.



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