MPC8280 datasheet(1136/1386 Pages) FREESCALE

1136 / 1386 page

ATM AAL2

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

33-30

Freescale Semiconductor

Table 33-10 describes the Switch RxBD fields.

33.4.4.7

SSSAR Rx Queue Descriptor

The SSSAR RxQD, as shown in Figure 33-20, points to the RxBD table and contains other parameters

specific to the SSSAR sublayer. This descriptor can belong to only one PHY | VP | VC | CID.

Table 33-10. Switch RxBD Field Descriptions

Offset

Bits

Name1

Boldfaced entries must be initialized by the user.

Description

0x00

E/R

Buffer Ready

Must be set to zero.

Not valid for switching mode, should be cleared to 0 upon initialization.

Wrap (final BD in table)

0 This is not the last BD in the RxBD table.

1 This is the last BD in the RxBD table of this current channel. After this buffer has been

used, the CP receives incoming data for this channel into the first BD in the table. The

number of RxBDs in this table is programmable and is determined only by the W bit.

The current table cannot exceed 64 Kbytes.

Interrupt.

0 The CP will not issue an interrupt after this buffer is serviced.

1 The CP will issue an interrupt after this buffer is serviced if the RBM bit in the RxQD is

set.

4–6

—

Reserved, should be cleared during initialization.

Uncompleted packet.

0 No error occurred in this packet and the complete packet has been received.

1 if R/E=1 a receive error occurred that caused this packet to be uncompleted. The

receive error type is reported to the interrupt queue. The transmitter will skip this

BD when in this state and continue to the next BD in the ring.

If R/E=0 a receiver has received the first part of a packet and is waiting for the rest of

it to be received on the next ATM cell.

8–15

CPS Packet

Header

Contains the beginning of the packet header. See Figure 33-10 for the CPS packet

header format. (see remark in next row)

0x02

—

CPS Packet

Header

(Receiver

CC)

Contains the rest of the packet header. The CP checks the packet HEC and if

appropriate, indicates a packet HEC error in an interrupt queue entry with CID = 0. See

Figure 33-10 for the CPS packet header format.

In case of a “stuck” receiver in switch mode, where the BD ring in common to Tx and

Rx, this field indicates the last Receiver Channel Code number which has been

received. The terminology for “stuck” implies a receiver which started receiving a

packet and the rest of the packet hasn’t been received.When the receiver is in a “stuck”

state the entry: CPS Packet Header is not valid. If the Time-out mechanism is being

used this field is being used internally by the CPM.

0x04

—

RXBDPTR

Rx data buffer pointer. Points to the address of the associated buffer. There are no

byte-alignment requirements for the buffer, and it may reside in either internal or

external memory. This value is not modified by the CP.

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