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MPC8280 Datasheet(PDF) 1135 Page - Freescale Semiconductor, Inc |
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MPC8280 Datasheet(HTML) 1135 Page - Freescale Semiconductor, Inc |
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1135 / 1386 page ![]() ATM AAL2 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 33-29 Table 33-9 describes the CPS switch RxQD fields. 33.4.4.6 SWITCH Receive/Transmit Buffer Descriptor (RxBD) The switch buffer structure consists of a BD table that points to data buffers. The RxBDs contain, apart from the buffer pointer, the packet header, as shown in Figure 33-19. The buffers contain the packet payload. This BD is common to the receiver and the transmitter. 0 7 8 11 12 13 14 15 Offset + 0x00 TX CID — RBM PPD SubType Offset + 0x02 TxQD Pointer Figure 33-18. CPS Switch Rx Queue Descriptor Table 33-9. CPS Switch RxQD Field Descriptions Offset Bits Name1 1 Boldfaced entries must be initialized by the user. Description 0x00 0–7 TX CID Translation CID. The received CID is saved in a TX Queue with this new CID number. 8–11 — Reserved, should be cleared during initialization. 12 RBM Receive buffer mask 0 Disable receive buffer interrupt 1 Enable receive buffer interrupt 13 PPD Partial packet discard 0 Normal mode 1 When a buffer-not-ready event causes a packet to be discarded, the remainder of the SSSAR SDU is also discarded. This allows for better performance for switched channels that implement SSSAR. 14–15 SubType Sublayer type. Should be 01 (CPS switched) for this descriptor. 00 CPS sublayer 01 CPS switched 10 SSSAR 11 Reserved 0x02 — TxQD Pointer Points to the TxQD into which the packets of this CID are stored and later sent. 0 1 2 3 4 5 6 7 8 15 Offset + 0x00 E/R 0 W I — UP CPS Packet Header Offset + 0x02 Packet Header (Receiver CC) Offset + 0x04 Rx Data Buffer Pointer (RXDBPTR) Offset + 0x06 Figure 33-19. Switch Receive/Transmit Buffer Descriptor |
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