MPC8280 datasheet(1144/1386 Pages) FREESCALE

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ATM AAL2

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

33-38

Freescale Semiconductor

33.7

AAL2 Exceptions

For each VC, four circular interrupt queues are available. By programming RCT[INTQ] and TCT[INTQ]

for each VC, the user assigns an interrupt queue number.

When one of the CIDs generates an interrupt request, the CP writes a new entry to the interrupt queue

containing the ATM channel number, the CID and a description of the exception. Because CID = 0 is a

unique CID number, it is used to specify that the event is related to the VC rather than the CID. As with

all ATM exceptions, the valid (V) bit is then set and INTQ_PTR is incremented. When INTQ_PTR reaches

a location with the W bit set, it wraps to the first entry in the queue. More details can be found in

Section 31.11, “ATM Exceptions.”

An interrupt entry for a CID is shown in Figure 33-23.

Table 33-14 describes the interrupt queue entry fields for a CID.

Offset + 0x00

—

CID

TBNR RXB BSY

TXB

RXF

Offset + 0x02

Channel Code (CC)

Figure 33-23. AAL2 Interrupt Queue Entry CID

≠ 0

Table 33-14. AAL2 Interrupt Queue Entry CID

≠ 0 Field Descriptions

Offset

Bits

Name

Description

0x00

Valid interrupt entry

0 This interrupt queue entry is free and can be used by the CP.

1 This interrupt queue entry is valid. The host should read this interrupt and clear this bit.

1—

—

Wrap bit. When set, this is the last interrupt entry in the circular table. During initialization,

the host must clear all W bits in the table except the last one, which must be set.

3–10

CID

CID number. The exception occurred for this CID.

TBNR

Tx buffer not ready interrupt. This interrupt is issued when the CP tries to open a TxBD,

which is not ready (R = 0). This interrupt is sent only if TxQD[BNM] = 1. The interrupt has

an associated channel code and CID.

Note: The CID number that is placed in the interrupt queue is the one currently located in

the last BD. Because the CID is not updated when the BD is not ready, the CID value

is the one extracted from this BD when it was last processed and transmitted. If the

BD is never processed and the BD was cleared, the CID value could be zero.

RXB1

1 These interrupt queue fields are defined differently for other AAL types. Refer toTable 31-42 for more information.

Rx buffer interrupt. This interrupt is issued when the I bit is set for an RxBD and the

RxQD[RBM] bit is set. This interrupt has an associated channel code and CID.

BSY

Busy condition. The RxBD table associated with this channel’s CID is busy. Packets were

discarded due to this condition.

TXB

Transmit buffer interrupt. This interrupt is issued when the TxBD[I] bit is set. This interrupt

is sent only if TxQD[TBM] is set. This interrupt has an associated channel code and CID.

RXF1

Receive SSSAR SDU (frame). An SSSAR frame belonging to this channel’s CID has been

received. This interrupt is sent only if RxQD[RFM]=1.

0x02

—

Channel code specifies the ATM channel number associated with this interrupt.

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