MPC8280 datasheet(1319/1386 Pages) FREESCALE

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Parallel I/O Ports

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

41-3

41.2.3

Port Data Direction Registers (PDIRA–PDIRD)

The port data direction register(PDIR), shown in Figure 41-3, is cleared at system reset.

Table 41-2 describes PDIR fields.

Field D01

D11

D21

D31

D10

D11

D12

D13

D14

D15

Reset

—

R/W

Addr

0x10D10 (PDATA), 0x10D30 (PDATB), 0x10D50 (PDATC), 0x10D70 (PDATD)

Field D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26

D27

D28

D29

D30

D31

Reset

—

R/W

Addr

0x10D12 (PDATA), 0x10D32 (PDATB), 0x10D52 (PDATC), 0x10D72 (PDATD)

1 These bits are valid for PDATA and PDATC only

Figure 41-2. Port Data Registers (PDATA–PDATD)

123

Field DR01 DR11 DR21 DR31 DR4

DR5

DR6

DR7

DR8

DR9 DR10 DR11 DR12 DR13 DR14 DR15

Reset

0000_0000_0000_0000

R/W

Addr

0x10D00 (PDIRA), 0x10D20 (PDIRB), 0x10D40 (PDIRC), 0x10D60 (PDIRD)

Field DR16 DR17 DR18 DR19 DR20 DR21 DR22 DR23 DR24 DR25 DR26 DR27 DR28 DR29 DR30 DR31

Reset

0000_0000_0000_0000

R/W

Addr

0x10D02 (PDIRA), 0x10D22 (PDIRB), 0x10D42 (PDIRC), 0x10D62 (PDIRD)

1 These bits are valid for PDIRA and PDIRC only

Figure 41-3. Port Data Direction Register (PDIR)

Table 41-2. PDIR Field Descriptions

Bits

Name

Description

0–31

Direction. Indicates whether a pin is used as an input or an output. Note that bits DR0–DR3 are valid

for PDIRA and PDIRC only.

0 The corresponding pin is an input or is bidirectional.

1 The corresponding pin is an output.

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