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ACT8846 Datasheet(PDF) 52 Page - Qorvo, Inc

Part # ACT8846
Description  Advanced PMU for Multi-core Application Processors
PDF  63 Pages
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Manufacturer  QORVO [Qorvo, Inc]
Direct Link  https://www.qorvo.com/
Logo QORVO - Qorvo, Inc

ACT8846 Datasheet(HTML) 52 Page - Qorvo, Inc

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ACT8846
Advanced PMU for Multi-core
Application Processors
Data Sheet Rev. 13.0, Nov. 11, 2019 | Subject to change without notice
52 of 63
www.qorvo.com
CMI 112: ACT8846QM112
CMI112 is optimized to power the Arm® Cortex® A7 processor. All buck converters are configured for forced PWM
mode, but can be reconfigured to operate in power saving mode if desired.
Sequencing
Rail
VSET0 Voltage (V)
VSET1 Voltage (V)
Sequencing Input Trigger
StartUp Delay (us)
Soft-Start (us)
OUT1
1.8
1.8
OUT7
0
400
OUT2
0.9
0.9
GPIO1
500
400
OUT3
1.2
1.2
OUT11
500
400
OUT4
3.0
3.0
I2C
0
400
OUT5
3.3
n/a
I2C
0
140
OUT6
1.8
n/a
I2C
0
140
OUT7
1.8
n/a
OUT2
500
140
OUT8
3.3
n/a
OUT3
500
140
OUT9
3.3
n/a
OUT8
1000
140
OUT10
3.3
n/a
OUT8
500
100
OUT11
2.5
n/a
OUT1
500
100
OUT12
3.3
n/a
I2C
0
100
OUT13
1.8
n/a
Always On
0
100
Hardware Configuration
PWRHLD and PWREN must be connected together in CMI 112.
GPIO1 must be directly connected to OUT13 in CMI 112.
Startup
The ACT8846QM112-T has two startup sequences. The first is pushbutton startup. Asserting nPBIN low starts the
startup sequence. nPBIN must stay low until after PWRHLD and PWREN are asserted high by an external source,
usually a uP. If nPBIN goes high before PWRHLD goes high, the IC shuts down all outputs. The second startup
sequence is with the PWREN and PWRHLD pins. After input power is applied, asserting PWREN high starts the startup
sequence. Note that nPBIN should stay high in this application. In both startup conditions, OUT4/5/6/12 are off by default,
but can be enabled via I2C.
Power Save Mode
All buck regulators are programmed for forced PWM mode. This provides improved load transient response and
maintains a constant output voltage ripple across the full load range.



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