ADF4382ABCCZ datasheet(28/82 Pages) AD

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Data Sheet

ADF4382A

THEORY OF OPERATION

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Rev. A | 28 of 82

Figure 55. VCO Calibration Block

The following calibration timeout bit fields must be programmed for

autocalibration:

►

CAL_VTUNE_TO: At the beginning of the calibration, VTUNE

is precharged to a nominal voltage, which is dependent on the

temperature of operation. CAL_VTUNE_TO sets the precharge

time as follows:

CAL

_VTUNE_TO = Ceiling

CAL

_VTUNE_TO Time × fPFD

2DCLK_DIV1

(36)

The largest value capacitor in the loop filter directly affects

the time taken to precharge to VTUNE. Refer to the Calibra-

tion Time Performance Consideration section to calculate the

CAL_VTUNE_TO time required. This time is used as the Target

VTUNE Calibration Timeout.

►

CAL_COUNT_TO: This is used to calculate the target band de-

cision timeout. During autocalibration, there are nine band deci-

sions to be made to select the final band of operation for the se-

lected frequency. CAL_COUNT_TO is used to program the time

taken for each band decision. This time affects the calibration

accuracy. See Table 21 for the recommended CAL_COUNT_TO

time. Use the following equation to set the decision time of each

band:

CAL

_COUNT_TO = Ceiling

CAL_COUNT_TO Time ×

fPFD

2DCLK_DIV1×16

(37)

►

CAL_VCO_TO: This bit field is used to set the target VCO

frequency settling timeout after each band decision. As per Table

21 the recommended CAL_VCO_TO time is 1μs. To set this

time, use the following equation:

CAL

_VCO_TO = Ceiling

CAL_VCO_TO Time × fPFD

2DCLK_DIV1

(38)

To perform a VCO calibration, set up the following several registers

as outlined in the following procedure:

1. Set DCLK_DIV1 and DCLK_MODE to the values listed in Table

20 and record fDIV_RCLK for later use.

2. Calculate and set the minimum required values for

CAL_VTUNE_TO, CAL_VCO_TO, and CAL_COUNT_TO as

per their corresponding formulas previously described in this

section.

3. Set the N_INT, RFOUT_DIV, and R_DIV bits and the

EN_RDBLR bit by programming Register 0x010 last. Any writes

to Register 0x010 start the VCO autocalibration.

4. Monitor the ADC_BUSY bit and FSM_BUSY bit (Register

0x058, Bit 2 and Bit 3, respectively). The calibration is finished

when ADC_BUSY transitions from high to low, followed with

FSM_BUSY transitioning from high to low.

5. After the VCO calibration is complete, disable the calibra-

tion clocks to limit unwanted spurious content by setting

EN_DRCLK = EN_DNCLK = 0.

Table 20. DCLK_DIV1 and DCLK_MODE Setup

fPFD (MHz)

DCLK_DIV1

DCLK_MODE

fDIV_RCLK (MHz)

≤11

fFPD

>11 and ≤160

fFPD/2

>160 and ≤320

fPFD/4

>320

fPFD/8

Total Autocalibration Time

Use each of the calibration timeout values to calculate the total

autocalibration time as follows:

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