ADF4382ABCCZ datasheet(36/82 Pages) AD

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Data Sheet

ADF4382A

APPLICATIONS INFORMATION

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Rev. A | 36 of 82

Figure 69. DC-Coupled 3.3 V Single-Ended Logic to LVDS Input (Set

SYNC_SEL = 1)

OUTPUT PHASE NOISE CHARACTERISTICS

In-Band Output Phase Noise

Use the following equations to calculate the in-band phase noise

floor (LOUT) produced at fOUT:

LOUT =

LNORM+10×log10fPFD +20×log10 fOUTfPFD (49)

LOUT = LNORM+10×log10fPFD +20

×log10 NO

(50)

Output Phase Noise Due to 1/f Noise

In-band phase noise at low offset frequencies can be influenced

by the 1/f noise of the ADF4382A depending on the fPFD. Use the

normalized in-band 1/f noise (L1/f) of −287 dBc/Hz to approximate

the output 1/f phase noise at a given frequency offset (fOFFSET) as

follows:

LOUT1/f = L1/f+20×log10fOUT −10

×log10fOFFSET

(51)

Unlike the in-band noise floor (LOUT), the 1/f noise (LOUT(1/f)) does

not change with fPFD and is not constant over offset frequency. For

an example of in-band phase noise for fPFD equal to 100 MHz and

500 MHz for integer mode, see Figure 70. The total phase noise

is the summation of LOUT and LOUT(1/f) calculated by the following

formula:

LOUTTOTAL=

10×log1010LOUT/10+10LOUT1/f/10 (52)

Figure 70. Theoretical In-Band Phase Noise, fOUT = 10 GHz

OUTPUT PHASE SYNCHRONIZATION OF

MULTIPLE ADF4382A DEVICES

To synchronize multiple ADF4382A devices, use one of the follow-

ing two methods:

►

EZSyncTM method, which uses SPI register writes for synchroni-

zation

►

Timed synchronization method , which uses the SYNCx pin on

the ADF4382A for synchronization

EZSync Method

The EZSync synchronization method allows synchronization of the

output phases of multiple devices without the need for a separate

synchronization signal, which has the advantage of reducing PCB

layout complexity in systems using multiple ADF4382A devices.

EZSync relies on sending a synchronization request through the

SPI interface by setting SW_SYNC = 1 instead of the SYNC pin.

The problem with sending the request over SPI are that the SPI is

a slow protocol and does not have any time accuracy. Sending the

request in the same reference period is also another challenge and

not possible for a huge number of ADF4382A devices used. With

EZSync, these problems are solved by starting and stopping the

DC-coupled reference signal glitchlessly, which removes the setup

and hold time concern with sending a request through the SPI.

The reference signals must stop and start accurately and without

any glitch or without any runt pulse. The clock generation and

distribution devices from Analog Devices, such as the HMC7044B,

are recommended as these devices are compatible with EZSync.

The following steps outline the procedure to perform an EZSync

with two ADF4382A devices (assumes the hardward is set up as

per Figure 71)

1. Set up the HMC7044B for EZSync configuration as follows:

a. Set the channel that is used as a reference to the

ADF4382A to dynamic mode. e.g. for channel 0 set register

0x00C8 to 0xFF.

ADF4382ABCCZ Datasheet(PDF) 36 Page - Analog Devices

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