ADF4382ABCCZ datasheet(55/82 Pages) AD

55 / 82 page

Data Sheet

ADF4382A

analog.com

Rev. A | 55 of 82

Address: 0x02F, Reset: 0x00, Name: REG002F

Table 68. Bit Descriptions for REG002F

Bits

Bit Name

Description

Reset

Access

BST_REF

Gain boost for low amplitude sinewave reference input (REF_SEL = 1).

0x0

R/W

0: Use for large ref input signals > 8dBm when REF_SEL = 1.

1: Use for ref input signals < 8dBm when REF_SEL = 1.

FILT_REF

Select Noise Filter for Sinewave Ref Input Buffer.

0x0

R/W

0: noise filter off.

1: noise filter on.

[5:0]

RDBLR_DC

Reference Doubler Output Duty-cycle. See Table 11.

0x0

R/W

Address: 0x030, Reset: 0x00, Name: REG0030

Table 69. Bit Descriptions for REG0030

Bits

Bit Name

Description

Reset

Access

MUTE_NCLK

Mutes the N-divider output to digital block. Set to 0 for normal operation.

0x0

R/W

RESERVED

Reserved.

0x0

R/W

REF_SEL

Select CML reference input or sine-wave and slow slew-rate reference input.

0x0

R/W

0: CML reference input.

1: Sinewave or slow slew-rate ref input.

INV_RDBLR

Invert the Reference Doubler Output. See Table 11.

0x0

R/W

0: Doubler Output Not Inverted.

1: Doubler Output Inverted.

[3:0]

RDBLR_DEL_SEL

Sets the Doubler Pulse Width. See Table 11.

0x0

R/W

Address: 0x031, Reset: 0x00, Name: REG0031

Table 70. Bit Descriptions for REG0031

Bits

Bit Name

Description

Reset

Access

[7:5]

SYNC_DEL

Sets the programmable input delay for the synchronization path. See Table 26.

0x0

R/W

RST_SYS

Reset Digital Except SPI and Registers to POR State.

0x0

R/W

0: reset inactive.

1: reset active.

EN_ADC_CLK

Enable the ADC Clock.

0x0

R/W

0: disable ADC clock.

1: enable ADC clock.

RESERVED

Reserved.

0x0

R/W

REG31_RSV1

Reserved. ADF4382A register map provides reserved register settings.

0x0

R/W

DCLK_MODE

Divide RCLK and NCLK frequency by factor of 2 during VCO calibration.

0x0

R/W

0: disable frequency division.

1: enable frequency division.

Address: 0x032, Reset: 0x00, Name: REG0032

Table 71. Bit Descriptions for REG0032

Bits

Bit Name

Description

Reset

Access

RESERVED

Reserved.

0x0

R/W

REG32_RSV6

Reserved. ADF4382A register map provides reserved register settings.

0x0

R/W

DEL_MODE

Select the Adjustment Mode to Use.

0x0

R/W

ADF4382ABCCZ Datasheet(PDF) 55 Page - Analog Devices

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