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INA203-Q1

SBOS539A – DECEMBER 2010 – REVISED APRIL 2016

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(1)

Hysteresis refers to the threshold (the threshold specification applies to a rising edge of a noninverting input) of a falling edge on the

noninverting input of the comparator; refer to Figure 1.

(2)

Specified by design; not production tested.

(3)

See the Comparator Maximum Input Voltage Range section.

(4)

The comparator response time specified is the interval between the input step function and the instant when the output crosses 1.4 V.

(5)

The CMP1 RESET input has an internal 2 M

Ω (typical) pull-down. Leaving the CMP1 RESET open results in a LOW state, with

transparent comparator operation.

(6)

The Comparator 2 delay applies to both rising and falling edges of the comparator output.

7.6

Electrical Characteristics: Comparator

At TA = +25°C, VS = +12 V, VCM = +12 V, VSENSE = 100 mV, RL = 10 kΩ to GND, and RPULL-UP = 5.1 kΩ each connected from

CMP1 OUT and CMP2 OUT to VS, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OFFSET VOLTAGE

Offset voltage

Comparator common-mode voltage = threshold voltage

2

mV

Offset voltage drift, comparator 1

TA = –40°C to +125°C

±2

μV/°C

Offset voltage drift, comparator 2

TA = –40°C to +125°C

5.4

μV/°C

Threshold

Rising Edge on Non-Inverting input, TA = +25°C

590

608

620

mV

Over temperature

TA = –40°C to +125°C

586

625

mV

Hysteresis(1), CMP1

TA = –40°C to +85°C

–8

mV

Hysteresis(1), CMP2

TA = –40°C to +85°C

8

mV

INPUT BIAS CURRENT(2)

CMP1 IN+, CMP2 IN+

0.005

10

nA

Over temperature

TA = –40°C to +125°C

15

nA

INPUT IMPEDANCE

Pins 3 and 6

10

k

Ω

INPUT RANGE

CMP1 IN+ and CMP2 IN+

0 V to VS – 1.5 V

V

Pins 3 and 6(3)

0 V to VS – 1.5 V

V

OUTPUT

Large-signal differential voltage gain

CMP VOUT 1 V to 4 V, RL ≥ 15 kΩ connected to 5 V

200

V/mV

High-level output current

VID = 0.4 V, VOH = VS

0.0001

1

μA

Low-level output voltage

VID = –0.6 V, IOL = 2.35 mA

220

300

mV

RESPONSE TIME(4)

Comparator 1

RL to 5 V, CL = 15 pF, 100 mV input step with 5 mV overdrive

1.3

μs

Comparator 2

RL to 5 V, CL = 15 pF, 100 mV input step with 5 mV overdrive,

CDELAY pin open

1.3

μs

RESET

RESET threshold(5)

1.1

V

Logic input impedance

2

M

Ω

Minimum RESET pulse width

1.5

μs

RESET propagation delay

3

μs

Comparator 2 delay equation(6)

CDELAY = tD/5

μF

tD

Comparator 2 delay

CDELAY = 0.1 μF

0.5

s