U2

U1

0.6V

1.2V

I2

120nA

I1

120nA

C

DELAY

13

INA203-Q1

www.ti.com

SBOS539A – DECEMBER 2010 – REVISED APRIL 2016

Product Folder Links: INA203-Q1

Submit Documentation Feedback

Copyright © 2010–2016, Texas Instruments Incorporated

Feature Description (continued)

NOTE

I1 and I2 cannot be turned on simultaneously; I1 corresponds to a U1 low output and I2

corresponds to a U1 high output.

Using an initial assumption that the U1 output is low, I1 is on, then U2 +IN is zero. If U1 goes high, I2 supplies

120 nA to CDELAY. The voltage at U2 +IN begins to ramp toward a 0.6-V threshold. When the voltage crosses this

threshold, the U2 output goes high while the voltage at U2 +IN continues to ramp up to a maximum of 1.2 V

when given sufficient time (twice the value of the delay specified for CDELAY). This entire sequence is reversed

when the comparator outputs go low, so that returning to low exhibits the same delay.

Figure 27. Simplified Model of The Comparator 2 Delay Circuit

It is important to note the behavior of the Comparator 2 when the events at the inputs occur more rapidly than

the set delay timeout. For example, when the U1 output goes high (turning on I2), but returns low (turning I1

back on) prior to reaching the 0.6 V transition for U2. The voltage at U2 +IN ramps back down at a rate

determined by the value of CDELAY, and only returns to zero if given sufficient time.

In essence, when analyzing Comparator 2 for behavior with events more rapid than its delay setting, use the

model shown in Figure 27.

8.3.3 Comparator Maximum Input Voltage Range

The maximum voltage at the comparator input for normal operation is up to (VS) – 1.5 V. There are special

considerations when overdriving the reference inputs (pins 3 and 6). Driving either or both inputs high enough to

drive 1 mA back into the reference introduces errors into the reference. Figure 28 shows the basic input

structure. A general guideline is to limit the voltage on both inputs to a total of 20 V. The exact limit depends on

the available voltage and whether either or both inputs are subject to the large voltage. When making this

determination, consider the 20 k

Ω from each input back to the comparator. Figure 29 shows the maximum input

voltage that avoids creating a reference error when driving both inputs (an equivalent resistance back into the

reference of 10 k

Ω).