EMC2103 datasheet(61/84 Pages) SMSC

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RPM-Based Fan Controller with HW Thermal Shutdown

Datasheet

SMSC EMC2103

Revision 0.85 (01-29-08)

DATASHEET

setting that will maintain fan operation is a useful way to avoid potential fan oscillations as the control

circuitry attempts to drive it at a level that cannot support fan operation.

The Fan Minimum Drive Register is software locked.

6.28

Valid TACH Count Register

The Valid TACH Count Register store the maximum TACH Reading Register value to indicate that the

the fan is spinning properly. The value is referenced at the end of the Spin Up Routine to determine

if the fan has started operating and decide if the device needs to retry.

See Equation [4] for translating the count to an RPM.

If the TACH Reading Register value exceeds the Valid TACH Count Register (indicating that the Fan

RPM is below the threshold set by this count), then a stalled fan is detected. In this condition, the

algorithm will automatically begin its Spin Up Routine.

APPLICATION NOTE: The automatic invoking of the Spin Up Routine only applies if the Fan Speed Control

Algorithm is used. If the FSC is disabled, then the device will only invoke the Spin Up Routine

when the PWM setting changes from 00h.

If a TACH Target setting is set above the Valid TACH Count setting, then that setting will be ignored

and the algorithm will use the current fan drive setting.

The Valid TACH Count Register is software locked.

6.29

Fan Drive Fail Band Registers

The Fan Drive Fail Band Registers store the number of tach counts used by the Fan Drive Fail

detection circuitry. This circuitry is activated when the fan drive setting high byte is at FFh. When it is

enabled, the actual measured fan speed is compared against the target fan speed.

This circuitry is used to indicate that the target fan speed at full drive is higher than the fan is actually

capable of reaching. If the measured fan speed does not exceed the target fan speed minus the Fan

Drive Fail Band Register settings for a period of time longer than set by the DRIVE_FAIL_CNTx[1:0]

bits then the DRIVE_FAIL status bit will be set and an interrupt generated.

Table 6.44 Valid TACH Count Register

ADDR

R/W

B7B6B5B4B3B2B1B0

DEFAULT

49h

R/W

Valid TACH

Count

4096

2048

1024

512

256

128

F5h

Table 6.45 Fan Drive Fail Band Registers

ADDR

R/W

DEFAULT

4Ah

R/W

Fan Drive

Fail Band

Low Byte

00h

4Bh

R/W

Fan Drive

Fail Band

High Byte

4096

2048

1024

512

256

128

00h

EMC2103 Datasheet(PDF) 61 Page - SMSC Corporation

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