STA339BW datasheet(45/78 Pages) STMICROELECTRONICS

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STA339BW

7.6.2

Invalid input detect mute enable

Setting the IDE bit enables this function, which looks at the input I2S data and automatically

mutes if the signals are perceived as invalid.

7.6.3

Binary output mode clock loss detection

Detects loss of input MCLK in binary mode and will output 50% duty cycle.

7.6.4

LRCK double trigger protection

Actively prevents double trigger of LRCLK.

7.6.5

Auto EAPD on clock loss

When active, issues a power device power down signal (EAPD) on clock loss detection.

7.6.6

IC power down

The PWDN register is used to place the IC in a low-power state. When PWDN is written

as 0, the output begins a soft-mute. After the mute condition is reached, EAPD is asserted

Table 47. Invalid input detect mute enable

Bit

R/W

RST

Name

Description

R/W

IDE

Setting of 1 enables the automatic invalid input

detect mute

Table 48. Binary output mode clock loss detection

Bit

R/W

RST

Name

Description

R/W

BCLE

Binary output mode clock loss detection enable

Table 49. LRCK double trigger protection

Bit

R/W

RST

Name

Description

R/W

LDTE

LRCLK double trigger protection enable

Table 50. Auto EAPD on clock loss

Bit

R/W

RST

Name

Description

R/W

ECLE

Auto EAPD on clock loss

Table 51. IC power down

Bit

R/W

RST

Name

Description

R/W

PWDN

0: IC power down low-power condition

1: IC normal operation

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