STA339BW datasheet(72/78 Pages) STMICROELECTRONICS

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Application

STA339BW

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DocID15251 Rev 8

Application

8.1

Application scheme for power supplies

Here in Figure 23 below is the typical application diagram for STA339BW showing the

power supply decoupling. Particular care has to be taken with the layout of the PCB. In

particular the 3.3

 resistors on the digital supplies (VDD_DIG) have to be placed as close

as possible to the device. This helps to prevent unwanted oscillation in the digital part of the

device due to the inductive tracks of the PCB. The same rule also applies to all the

decoulpling capacitors in order to limit spikes on all the supplies.

Figure 23. Application diagram

8.2

PLL filter

It is recommended to use the above scheme and values for the PLL filter to achieve the best

performance from the device in general applications. Note that the ground of this filter circuit

has to be connected to the ground of the PLL without any resistive path.

Concerning the component values, remember that the greater is the filter bandwidth, the

less is the lock time but the higher is the PLL output jitter.

STA339BW Datasheet(PDF) 72 Page - STMicroelectronics