STA339BW datasheet(46/78 Pages) STMICROELECTRONICS

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STA339BW

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to power down the power-stage, then the master clock to all internal hardware expect the

I2C block is gated. This places the IC in a very low power consumption state.

7.6.7

External amplifier power down

The EAPD register directly disables/enables the internal power circuitry.

When EAPD = 0, the internal power section is placed on a low-power state (disabled). This

7.7

Volume control registers (addr 0x06 - 0x0A)

7.7.1

Mute/line output configuration register

Line output is only active when OCFG = 00. In this case LOC determines the line output

configuration. The source of the line output is always the channel 1 and 2 inputs.

7.7.2

Master volume register

7.7.3

Channel 1 volume

Table 52. External amplifier power down

Bit

R/W

RST

Name

Description

R/W

EAPD

0: External power stage power down active

1: Normal operation

LOC1

LOC0

Reserved

C3M

C2M

C1M

MMUTE

00000000

Table 53. Line output configuration

LOC[1:0]

Line output configuration

Line output fixed - no volume, no EQ

Line output variable - CH3 volume effects line output, no EQ

Line output variable with EQ - CH3 volume effects line output

MV7

MV6

MV5

MV4

MV3

MV2

MV1

MV0

11111111

C1V7

C1V6

C1V5

C1V4

C1V3

C1V2

C1V1

C1V0

01100000

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