STA339BW datasheet(48/78 Pages) STMICROELECTRONICS

48 / 78 page

STA339BW

48/78

DocID15251 Rev 8

7.8

Audio preset registers (addr 0x0B and 0x0C)

7.8.1

Audio preset register 1 (addr 0x0B)

Using AMGC[3:0] bits, attack and release thresholds and rates are automatically configured

to properly fit application specific configurations. AMGC[3:2] is defined in register EQ

coefficients and DRC configuration register (addr 0x31) on page 66.

The AMGC[1:0] bits behave in two different ways depending on the value of AMGC[3:2].

When this value is 00 then bits AMGC[1:0] are defined below in Table 56.

Table 55. Channel volume as a function of CxV[7:0]

CxV[7:0]

Volume

00000000 (0x00)

+48 dB

00000001 (0x01)

+47.5 dB

00000010 (0x02)

+47 dB

……

01011111 (0x5F)

+0.5 dB

01100000 (0x60)

0 dB

01100001 (0x61)

-0.5 dB

……

11010111 (0xD7)

-59.5 dB

11011000 (0xD8)

-60 dB

11011001 (0xD9)

-61 dB

11011010 (0xDA)

-62 dB

……

11101100 (0xEC)

-80 dB

11101101 (0xED)

Hard channel mute

……

11111111 (0xFF)

Hard channel mute

Reserved

AMGC[1]

AMGC[0]

Reserved

00000000

Table 56. Audio preset gain compression/limiters selection for AMGC[3:2] = 00

AMGC[1:0]

Mode

User programmable GC

AC no clipping 2.1

AC limited clipping (10%) 2.1

DRC night-time listening mode 2.1

STA339BW Datasheet(PDF) 48 Page - STMicroelectronics

STA339BW Datasheet(HTML) 48 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78

Datasheet Download

Link URL