STA339BW datasheet(34/78 Pages) STMICROELECTRONICS

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STA339BW

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7.3

Configuration register C (addr 0x02)

7.3.1

FFX power output mode

The FFX power output mode selects how the FFX output timing is configured.

Different power devices use different output modes.

7.3.2

FFX compensating pulse size register

OCRB

Reserved

CSZ3

CSZ2

CSZ1

CSZ0

OM1

OM0

10011111

Table 24. FFX power output mode

Bit

R/W

RST

Name

Description

R/W

OM0

Selects configuration of FFX output.

R/W

OM1

Table 25. Output modes

OM[1,0]

Output stage mode

Drop compensation

Discrete output stage - tapered compensation

Full power mode

Variable drop compensation (CSZx bits)

Table 26. FFX compensating pulse size bits

Bit

R/W

RST

Name

Description

R/W

CSZ0

When OM[1,0] = 11, this register determines the size

of the FFX compensating pulse from 0 clock ticks to

15 clock periods.

R/W

CSZ1

R/W

CSZ2

R/W

CSZ3

Table 27. Compensating pulse size

CSZ[3:0]

Compensating pulse size

0000

0 ns (0 tick) compensating pulse size

0001

20 ns (1 tick) clock period compensating pulse size

……

1111

300 ns (15 tick) clock period compensating pulse size

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