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STA339BW Datasheet(PDF) 37 Page - STMicroelectronics |
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STA339BW Datasheet(HTML) 37 Page - STMicroelectronics |
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37 / 78 page ![]() DocID15251 Rev 8 37/78 STA339BW Register description 78 7.4.7 Zero-detect mute enable Setting the ZDE bit enables the zero-detect automatic mute. The zero-detect circuit looks at the data for each processing channel at the output of the crossover (bass management) filter. If any channel receives 2048 consecutive zero value samples (regardless of fs) then that individual channel is muted if this function is enabled. 7.4.8 Submix mode enable 7.5 Configuration register E (addr 0x04) 7.5.1 Max power correction variable 7.5.2 Max power correction Setting the MPC bit turns on special processing that corrects the STA339BW power device at high power. This mode should lower the THD+N of a full FFX system at maximum power output and slightly below. If enabled, MPC is operational in all output modes except tapered (OM[1,0] = 01) and binary. When OCFG = 00, MPC will not effect channels 3 and 4, the line- out channels. Table 35. Zero-detect mute enable Bit R/W RST Name Description 6 R/W 1 ZDE Setting of 1 enables the automatic zero-detect mute Table 36. Submix mode enable Bit R/W RST Name Description 7 R/W 0 SME 0: Sub Mix into Left/Right disabled 1: Sub Mix into Left/Right enabled D7 D6 D5 D4 D3 D2 D1 D0 SVE ZCE DCCV PWMS AME NSBW MPC MPCV 11000010 Table 37. Max power correction variable Bit R/W RST Name Description 0 R/W 0 MPCV 0: Use standard MPC coefficient 1: Use MPCC bits for MPC coefficient Table 38. Max power correction Bit R/W RST Name Description 1 R/W 1 MPC Setting of 1 enables Power Bridge correction for THD reduction near maximum power output. |
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