L99PM72PXP datasheet(77/128 Pages) STMICROELECTRONICS

77 / 128 page

L99PM72PXP

ST SPI

Doc ID 023553 Rev 3

77/128

6.1.2

Operating code definition

The <Write Mode> <Read Mode> and <Read and Clear Status> operations allow access to

the RAM of the device, i. e. to write to control registers or read status information.

A <Read and Clear Status> operation addressed to a device specific status register reads

back and subsequently clear this status register.

A <Read and Clear Status> operation with address 3FH clears all status registers (including

the Global Status Register). Configuration Register is read by this operation.

<Read Device Information> allows access to the ROM area which contains device related

information such as the product family, product name, silicon version, register width and

availability of a watchdog.

More detailed descriptions of the Device Information are available in ‘Read Device

Information’.

6.1.3

Global Status Register

6.1.4

Configuration register(f)

The <Configuration> register is accessible at RAM address 3FH.

For the Config Register, the 8 bits are located in the low byte (LSB).

The Configuration Register is implemented for compliance purpose to ST SPI Standard.

<WD Trigger>: This Bit is reserved to serve the watchdog.

Table 45.

Operating code definition

OC1

OC0

Meaning

Table 46.

Global status register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Global error

flag (GEF)

Comm

error

Not (chip reset

OR comm error)

TSD2

TSD1

V1 Fail

VS Fail

(OV/UV)

Fail

safe

See Section 6.2 for details.

Table 47.

Configuration register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

WD trigger

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