L99PM72PXP datasheet(32/128 Pages) STMICROELECTRONICS

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Detailed description

L99PM72PXP

32/128

Doc ID 023553 Rev 3

2.8

LIN Bus Interface

Features:

●

Speed communication up to 20kbit/s.

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LIN 2.1 compliant (SAEJ2602 compatible) transceiver.

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GND disconnection fail safe at module level.

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Off mode: does not disturb network.

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GND shift operation at system level.

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Micro controller Interface with CMOS compatible I/O pins.

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Internal Pull-up resistor

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Internal High Side Switch to disconnect Master Pull-up resistor in case of short circuit

of bus signal (b)

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ESD and transient immunity according to ISO7637 and EN / IEC61000-4-2

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Matched output slopes and propagation delay

In order to further reduce the current consumption in standby mode, the integrated LIN bus

interface offers an ultra low current consumption.

2.8.1

Error handling

The L99PM72PXP provides the following three error handling features which are not

described in the LIN Spec. V2.1, but are realized in different stand alone LIN transceivers /

micro controllers to switch the application back to normal operation mode.

At VS >VPOR (i.e. VS power-on reset threshold), the LIN transceiver is enabled.

The LIN transmitter is disabled in case of the following errors:

●

Dominant TxDL time out

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LIN permanent recessive

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Thermal Shutdown 1

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VS Over- / Undervoltage

The LIN receiver is not disabled in case of any failure condition.

Dominant TxDL time out

If TXDL is in dominant state (low) for more than 12 ms (typ) the transmitter is disabled, the

status bit is latched and can be read and optionally cleared by SPI. The transmitter remains

disabled until the status register is cleared. This feature can be disabled via SPI.

Permanent recessive

If TXDL changes to dominant (low) state but RXDL signal does not follow within 40 µs the

transmitter is disabled, the status bit is latched and can be read and optionally cleared by

SPI. The transmitter remains disabled until the status register is cleared.

Use of the Master Pull-up switch is optional.

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