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L99PM72PXP Datasheet(PDF) 79 Page - STMicroelectronics

Part # L99PM72PXP
Description  Advanced power management system IC with embedded LIN and high speed CAN transceiver supporting CAN Partial Networking
PDF  128 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

L99PM72PXP Datasheet(HTML) 79 Page - STMicroelectronics

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L99PM72PXP
ST SPI
Doc ID 023553 Rev 3
79/128
6.1.5
Address mapping
The RAM memory area consists of 16 bit registers.
For the device information (ROM memory area) the eight most significant bits of the memory
cell are used. The remaining 8 are zero.
All unused RAM and ROM addresses are read as ‘0’.
Note:
The register definition for RAM address 00H is unused. A register value of all 0 must cause
the device to enter a Fail-Safe state (interpreted as ‘SDI stuck to GND’ failure).
Note:
ROM address 3FH is unused. An attempt to access this address must be recognized as a
communication error (‘SDI stuck to VCC’ failure) and must cause the device to enter a
Fail-Safe state.
6.1.6
Write operation
The write operation starts with a Command Byte followed by 2, data bytes. The number of
data bytes is specified in the <SPI-frame-ID>.
Write command format
Table 48.
Address mapping
RAM
Address
Description
Access
ROM
Address
Description
Access
3FH
<Configuration>
R/W
3FH
Reserved
N/A
…
…
…
3EH
<SPI frame ID>
R
13H
Status Register 3
R
…Unused
N/A
12H
Status Register 2
R
11H
Status Register 1
R
……
…
06H
Control Register 6
R/W
05H
Control Register 5
R/W
04H
Control Register 4
R/W
03H
Control Register 3
R/W
03H
<product code 2>
R
02H
Control Register 2
R/W
02H
<product code 1>
R
01H
Control Register 1
R/W
01H
<silicon version>
R
00H
Reserved
R/W
00H
<ID Header>
R
Table 49.
Write command format: command byte
MSB
LSB
Op Code
Address
0
0
A5
A4
A3
A2
A1
A0



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