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L99PM72PXP Datasheet(PDF) 25 Page - STMicroelectronics |
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L99PM72PXP Datasheet(HTML) 25 Page - STMicroelectronics |
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25 / 128 page ![]() L99PM72PXP Detailed description Doc ID 023553 Rev 3 25/128 serve the watchdog by alternating the watchdog trigger bit within the safe trigger area (refer to Figure 32). A correct watchdog trigger signal immediately starts the next cycle. After 8 watchdog failures in sequence, the V1 regulator is switched off for 200 ms. If subsequently, 7 additional watchdog failures occur, the V1 regulator is completely turned off and the device goes into VBat_standby mode until a wakeup occurs. In case of a Watchdog failure, the outputs (RELx, OUTx, V2) are switched off and the device enters Fail_safe mode (i. e. all control registers are set to default values except the 'OUT3 control bit'). The following diagrams illustrate the Watchdog behavior of the L99PM72PXP. The diagrams are split into 3 parts. First diagram shows the functional behavior of the watchdog without any error. The second diagram covers the behavior covering all the error conditions, which can affect the watchdog behavior. Third diagram shows the transition in and out of FLASH mode. All 3 diagrams can be overlapped to get all the possible state transitions under all circumstances. For a better readability, they were split in normal operating, operating with errors and flash mode. Figure 10. Watchdog in normal operating mode (no errors) |
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