Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

Preview PDF HTML

L99PM72PXP Datasheet(PDF) 121 Page - STMicroelectronics

Part # L99PM72PXP
Description  Advanced power management system IC with embedded LIN and high speed CAN transceiver supporting CAN Partial Networking
PDF  128 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

L99PM72PXP Datasheet(HTML) 121 Page - STMicroelectronics

Back Button L99PM72PXP Datasheet HTML 117Page - STMicroelectronics L99PM72PXP Datasheet HTML 118Page - STMicroelectronics L99PM72PXP Datasheet HTML 119Page - STMicroelectronics L99PM72PXP Datasheet HTML 120Page - STMicroelectronics L99PM72PXP Datasheet HTML 121Page - STMicroelectronics L99PM72PXP Datasheet HTML 122Page - STMicroelectronics L99PM72PXP Datasheet HTML 123Page - STMicroelectronics L99PM72PXP Datasheet HTML 124Page - STMicroelectronics L99PM72PXP Datasheet HTML 125Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 121 / 128 page
background image
L99PM72PXP
ST SPI
Doc ID 023553 Rev 3
121/128
13
Device_state
State from which the device woke up
Bit is latched until a
“read and clear
access” after a
“read and clear
access”, the device
state is updated.
After a wake up,
device state is:
01: V1_standby
or
10: VBat_standby
12
Device state_2
Device state_1
State from
which the
device woke
up
00
Active
01
V1_standby
10
VBat_standby
11
Flash
11
V1_fail
V1 fail (V1 < 2 V for t > 2 µs) event occurred since last
read out
Bit is latched until a
“read and clear
access”
10
V1_restart_2
Number of TSD2 events which caused a restart of V1
regulator (7 TSD2 events forces the device into
VBat_standby)
Bits are not
clearable; is cleared
automatically if no
additional TSD2
event occurs within
1min.
9
V1_restart_1
8
V1_restart_0
7
WD_fail_3
Number of missing watchdog triggers (15 missing
watchdog trigger forces the device into VBat_standby)
Bits are not
clearable; is cleared
with a proper
Watchdog trigger
6
WD_fail_2
5
WD_fail_1
4
WD_fail_0
3
Forced_sleep_WD
Device was forced to VBat_standby mode because of
multiple watchdog errors
Bits are latched until
a read and clear
access
2
Forced_sleep_
TSD2_SHTV1
Device was forced to VBat_standby or multiple thermal
shutdown events or a short on V1 during startup.
1
WD_timer_state_1 Status of watchdog counter of selected watchdog
timing
Bits are not
clearable
0
WD_timer_state_0
WD_timer_state
_1
WD_timer_state
_0
Counter
0
0
0 – 33%
0
1
33 – 66%
1
1
66 – 100%
Table 141.
Status register 3, bits (continued)
Bit
Name
Comment
Information
storage



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com