DAC8554IPWR datasheet(21/34 Pages) TI2

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LDAC FUNCTIONALITY

ENABLE PIN

DAC8554

SLAS431B – JUNE 2005 – REVISED OCTOBER 2006

channels must be loaded with desired data before

LDAC

triggered.

After

low-to-high

LDAC

The DAC8554 offers both a software and hardware

transition, all DACs are simultaneously updated with

simultaneous

update

function.

The

DAC8554

the contents of the corresponding data buffers. If the

double-buffered architecture has been designed so

contents of a data buffer are not changed by the

that new data can be entered for each DAC without

serial interface, the corresponding DAC output will

disturbing

the

analog

outputs.

The

software

remain unchanged after the LDAC trigger.

simultaneous update capability is controlled by the

load 1 (LD1) and load 0 (LD0) control bits. By setting

load 1 = 1, all of the DAC registers will be updated

on the falling edge of the 24th clock signal. When the

For normal operation, the enable pin must be tied to

new data has been entered into the device, all of the

a logic low. If the enable pin is tied high, the

DAC outputs can be updated simultaneously and

DAC8554 stops listening to the serial port. This

synchronously with the clock.

feature can be useful for applications that share the

same serial port.

DAC8554 data updates are synchronized with the

falling edge of the 24th SCLK cycle, which follows a

falling

edge

SYNC.

For

such

synchronous

updates, the LDAC pin is not required and it must be

connected to GND permanently. The LDAC pin is

used as a positive edge triggered timing signal for

asynchronous DAC updates. Data buffers of all

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DAC8554IPWR Datasheet(PDF) 21 Page - Texas Instruments

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