SPC563M60X datasheet(94/128 Pages) STMICROELECTRONICS

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Electrical characteristics

SPC563M64x, SPC563M60x

94/128

DocID14642 Rev 12

4.13

Platform Flash controller electrical characteristics

DIFFmax

Maximum differential voltage

(DANx+ - DANx-) or (DANx- -

DANx+)

PREGAIN set

to 1X setting

–

(VRH -

VRL)/2

DIFFmax2

PREGAIN set

to 2X setting

–

(VRH -

VRL)/4

DIFFmax4

PREGAIN set

to 4X setting

–

(VRH -

VRL)/8

DIFFcmv

Differential input Common mode

voltage (DANx- + DANx+)/2(15)

(VRH -

VRL)/2 -

(VRH -

VRL)/2 +

Stop mode recovery time is the time from the setting of either of the enable bits in the ADC Control Register to the time that

the ADC is ready to perform conversions.Delay from power up to full accuracy = 8 ms.

At VRH – VRL = 5.12 V, one count = 1.25 mV. Without using pregain.

Below disruptive current conditions, the channel being stressed has conversion values of 0x3FF for analog inputs greater

then VRH and 0x0 for values less then VRL. Other channels are not affected by non-disruptive conditions.

Exceeding limit may cause conversion error on stressed channels and on unstressed channels. Transitions within the limit

do not affect device reliability or cause permanent damage.

Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate

resistance values using VPOSCLAMP = VDDA + 0.5 V and VNEGCLAMP = – 0.3 V, then use the larger of the calculated values.

Condition applies to two adjacent pins at injection limits.

Performance expected with production silicon.

All channels have same 10 k

 < Rs < 100 k; Channel under test has Rs=10 k; I

INJ=IINJMAX,IINJMIN.

TUE is tested by averaging 10 samples.

10. TUE is tested by averaging three samples.

11. These values can be significantly improved by using three samples of averaging. Input frequency of 1 kHz was used as the

reference for the Signal to Noise Ratio.

12. Variable gain is controlled by setting the PRE_GAIN bits in the ADC_ACR1-8 registers to select a gain factor of

1, 2, or

4. Settings are for differential input only. Tested at 1 gain. Values for other settings are guaranteed by as indicated.

13. At VRH – VRL = 5.12 V, one LSB = 1.25 mV.

14. Guaranteed 10-bit monotonicity.

15. Voltages between VRL and VRH will not cause damage to the pins. However, they may not be converted accurately if the

differential voltage is above the maximum differential voltage. In addition, conversion errors may occur if the common mode

voltage of the differential signal violates the Differential Input common mode voltage specification.

Table 30. eQADC conversion specifications (operating) (continued)

Symbol

Parameter

Value

Unit

min

max

Table 31. APC, RWSC, WWSC settings vs. frequency of operation(1)

Illegal combinations exist, all entries must be taken from the same row.

Target Max Frequency(2)

(MHz)

APC(3)

RWSC(3)

WWSC

000

001

010

011

All

111

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