SPC563M60X datasheet(15/128 Pages) STMICROELECTRONICS

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SPC563M64x, SPC563M60x

Overview

127



Periodic interrupt timer (PIT)

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32-bit wide down counter with automatic reload

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Four channels clocked by system clock

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One channel clocked by crystal clock

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Each channel can produce periodic software interrupt

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Each channel can produce periodic triggers for eQADC queue triggering

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One channel out of the five can be used as wake-up timer to wake device from low

power stop mode



System timer module (STM)

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32-bit up counter with 8-bit prescaler

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Clocked from system clock

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Four-channel timer compare hardware

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Each channel can generate a unique interrupt request

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Designed to address AUTOSAR task monitor function



Software watchdog timer (SWT)

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32-bit timer

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Clock by system clock or crystal clock

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Can generate either system reset or non-maskable interrupt followed by system

reset

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Enabled out of reset



Enhanced modular I/O system (eMIOS)

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16 timer channels (up to 14 channels in LQFP144)

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24-bit timer resolution

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3 selectable time bases plus shared time or angle counter bus from eTPU2

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DMA and interrupt request support

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Motor control capability



Second-generation enhanced time processor unit (eTPU2)

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Object-code compatible with eTPU—no changes are required to hardware or

software if only eTPU features are used

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Intelligent co-processor designed for timing control

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High level tools, assembler and compiler available

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32 channels (each channel has dedicated I/O pin in all packages)

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24-bit timer resolution

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14 KB code memory and 3 KB data memory

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Double match and capture on all channels

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Angle clock hardware support

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Shared time or angle counter bus with eMIOS

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DMA and interrupt request support

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Nexus Class 1 debug support

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eTPU2 enhancements

– Counters and channels can run at full system clock speed

– Software watchdog

– Real-time performance monitor

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