SPC563M60X datasheet(24/128 Pages) STMICROELECTRONICS

24 / 128 page

Overview

SPC563M64x, SPC563M60x

24/128

DocID14642 Rev 12



2 write/byte enable (WE[0:1]/BE[0:1]) signals



Configurable bus speed modes

–

system frequency

–

1/2 of system frequency

–

1/4 of system frequency



Optional automatic CLKOUT gating to save power and reduce EMI



Selectable drive strengths; 10 pF, 20 pF, 30 pF, 50 pF

2.3.7

SIU

The SPC563Mxx SIU controls MCU reset configuration, pad configuration, external

interrupt, general purpose I/O (GPIO), internal peripheral multiplexing, and the system reset

operation. The reset configuration block contains the external pin boot configuration logic.

The pad configuration block controls the static electrical characteristics of I/O pins. The

GPIO block provides uniform and discrete input/output control of the I/O pins of the MCU.

The reset controller performs reset monitoring of internal and external reset sources, and

drives the RSTOUT pin. Communication between the SIU and the e200z335 CPU core is

via the crossbar switch. The SIU provides the following features:



System configuration

–

MCU reset configuration via external pins

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Pad configuration control for each pad

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Pad configuration control for virtual I/O via DSPI serialization



System reset monitoring and generation

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Power-on reset support

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Reset status register provides last reset source to software

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Glitch detection on reset input

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Software controlled reset assertion



External interrupt

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11 interrupt requests

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Rising or falling edge event detection

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Programmable digital filter for glitch rejection

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Critical Interrupt request

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Non-Maskable Interrupt request



GPIO

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GPIO function on 80 I/O pins

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Virtual GPIO on 64 I/O pins via DSPI serialization (requires external

deserialization device)

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Dedicated input and output registers for setting each GPIO and Virtual GPIO pin



Internal multiplexing

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Allows serial and parallel chaining of DSPIs

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Allows flexible selection of eQADC trigger inputs

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Allows selection of interrupt requests between external pins and DSPI

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